8(g|1google,hayato-rev1google,hayatomediatek,mt8192 +7Google Hayato rev1aliases=/soc/ovl@14005000B/soc/ovl@14006000J/soc/ovl@14014000R/soc/rdma@14007000X/soc/rdma@14015000^/soc/serial@11002000oscillator0 fixed-clockfsclk26m"oscillator1 fixed-clockfsclk32kcpus+cpu@0cpuarm,cortex-a55pscisec3@cpu@100cpuarm,cortex-a55pscisec3@ cpu@200cpuarm,cortex-a55pscisec3@ cpu@300cpuarm,cortex-a55pscisec3@ cpu@400cpuarm,cortex-a76pscisf cpu@500cpuarm,cortex-a76pscisf cpu@600cpuarm,cortex-a76pscisfcpu@700cpuarm,cortex-a76pscisfcpu-mapcluster0core0core1 core2 core3 cluster1core0 core1 core2core3l2-cache0cachel2-cache1cachel3-cachecacheidle-statespscicpu-sleep-larm,idle-state)7:J cpu-sleep-barm,idle-state)#:Jcluster-sleep-larm,idle-state)<:J\cluster-sleep-barm,idle-state)(:J pmu-a55arm,cortex-a55-pmu [pmu-a76arm,cortex-a76-pmu [psci arm,psci-1.0smctimerarm,armv8-timer @[   s]@soc+ simple-busfinterrupt-controller@c000000 arm,gic-v3m~    [ ppi-partitionsinterrupt-partition-0 interrupt-partition-1 syscon@10000000 mediatek,mt8192-topckgensysconfsyscon@10001000 mediatek,mt8192-infracfgsysconfsyscon@10003000mediatek,mt8192-pericfgsyscon0f,pinctrl@10005000mediatek,mt8192-pinctrlP]iocfg0iocfg_rmiocfg_bmiocfg_bliocfg_briocfg_lmiocfg_lbiocfg_rtiocfg_ltiocfg_tleint[m I2S_DP_LRCKIS_DP_BCLKI2S_DP_MCLKI2S_DP_DATAOUTSAR0_INT_ODLEC_AP_INT_ODLEDPBRDG_INT_ODLDPBRDG_INT_ODLDPBRDG_PWRENDPBRDG_RST_ODLI2S_HP_MCLKI2S_HP_BCKI2S_HP_LRCKI2S_HP_DATAINAP_FLASH_WP_LTRACKPAD_INT_ODLEC_AP_HPD_ODSD_CD_ODLHP_INT_ODL_ALCEN_PP1000_DPBRDGAP_GPIO20TOUCH_INT_L_1V8UART_BT_WAKE_ODLAP_GPIO23AP_SPI_FLASH_CS_LAP_SPI_FLASH_CLKEN_PP3300_DPBRDG_DXAP_SPI_FLASH_MOSIAP_SPI_FLASH_MISOI2S_HP_DATAOUTAP_GPIO30I2S_SPKR_MCLKI2S_SPKR_BCLKI2S_SPKR_LRCKI2S_SPKR_DATAINI2S_SPKR_DATAOUTAP_SPI_H1_TPM_CLKAP_SPI_H1_TPM_CS_LAP_SPI_H1_TPM_MISOAP_SPI_H1_TPM_MOSIBL_PWMEDPBRDG_PWRENEDPBRDG_RST_ODLEN_PP3300_HUBHUB_RST_LSD_CLKSD_CMDSD_DATA3SD_DATA0SD_DATA2SD_DATA1PCIE_WAKE_ODLPCIE_RST_LPCIE_CLKREQ_ODLSPMI_SCLSPMI_SDAAP_GOODUART_DBG_TX_AP_RXUART_AP_TX_DBG_RXUART_AP_TX_BT_RXUART_BT_TX_AP_RXMIPI_DPI_D0_RMIPI_DPI_D1_RMIPI_DPI_D2_RMIPI_DPI_D3_RMIPI_DPI_D4_RMIPI_DPI_D5_RMIPI_DPI_D6_RMIPI_DPI_D7_RMIPI_DPI_D8_RMIPI_DPI_D9_RMIPI_DPI_D10_RMIPI_DPI_DE_RMIPI_DPI_D11_RMIPI_DPI_VSYNC_RMIPI_DPI_CLK_RMIPI_DPI_HSYNC_RPCM_BT_DATAINPCM_BT_SYNCPCM_BT_DATAOUTPCM_BT_CLKAP_I2C_AUDIO_SCLAP_I2C_AUDIO_SDASCP_I2C_SCLSCP_I2C_SDAAP_I2C_WLAN_SCLAP_I2C_WLAN_SDAAP_I2C_DPBRDG_SCLAP_I2C_DPBRDG_SDAEN_PP1800_DPBRDG_DXEN_PP3300_EDP_DXEN_PP1800_EDPBRDG_DXEN_PP1000_EDPBRDGSCP_JTAG0_TDOSCP_JTAG0_TDISCP_JTAG0_TMSSCP_JTAG0_TCKSCP_JTAG0_TRSTNEN_PP3000_VMC_PMUEN_PP3300_DISPLAY_DXTOUCH_RST_L_1V8TOUCH_REPORT_DISABLEAP_I2C_TRACKPAD_SCL_1V8AP_I2C_TRACKPAD_SDA_1V8EN_PP3300_WLANBT_KILL_LWIFI_KILL_LSET_VMC_VOLT_AT_1V8EN_SPKAP_WARM_RST_REQEN_PP3000_SD_S3AP_EDP_BKLTENAP_SPI_EC_CLKAP_SPI_EC_CS_LAP_SPI_EC_MISOAP_SPI_EC_MOSIAP_I2C_EDPBRDG_SCLAP_I2C_EDPBRDG_SDAMT6315_PROC_INTMT6315_GPU_INTUART_SERVO_TX_SCP_RXUART_SCP_TX_SERVO_RXBT_RTS_AP_CTSAP_RTS_BT_CTSUART_AP_WAKE_BT_ODLWLAN_ALERT_ODLEC_IN_RW_ODLH1_AP_INT_ODLMSDC0_CMDMSDC0_DAT0MSDC0_DAT2MSDC0_DAT4MSDC0_DAT6MSDC0_DAT1MSDC0_DAT5MSDC0_DAT7MSDC0_DSLMSDC0_CLKMSDC0_DAT3MSDC0_RST_LSCP_VREQ_VAOAUD_DAT_MOSI2AUD_NLE_MOSI1AUD_NLE_MOSI0AUD_DAT_MISO2AP_I2C_SAR_SDAAP_I2C_SAR_SCLAP_I2C_PWR_SCLAP_I2C_PWR_SDAAP_I2C_TS_SCL_1V8AP_I2C_TS_SDA_1V8SRCLKENA0SRCLKENA1AP_EC_WATCHDOG_LPWRAP_SPI0_MIPWRAP_SPI0_CSNPWRAP_SPI0_MOPWRAP_SPI0_CKAP_RTC_CLK32KAUD_CLK_MOSIAUD_SYNC_MOSIAUD_DAT_MOSI0AUD_DAT_MOSI1AUD_DAT_MISO0AUD_DAT_MISO1cr50-irq-default-pins&pins-gsc-ap-int-odl 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buck_vmodem,vmodem;S*kbuck_vpu,vpu;S7k buck_vcore,vcore;S k buck_vs2,vs2; 5Sjkbuck_vpa,vpa; S7k,buck_vproc2,vproc2;S7Lk buck_vproc1,vproc1;S7Lk buck_vcore_sshub ,vcore_sshub;S7buck_vgpu11_sshub ,vgpu11_sshub;Sldo_vaud18,vaud18;w@Sw@kldo_vsim1,vsim1;S/M`ldo_vibr,vibr;OS2Zldo_vrf12,vrf12;S ldo_vusb,vusb;-S-kldo_vsram_proc2 ,vsram_proc2; SLkldo_vio18,vio18;Skldo_vcamio,vcamio;Sldo_vcn18,vcn18;w@Sw@kldo_vfe28,vfe28;*S*kxldo_vcn13,vcn13; S ldo_vcn33_1_bt ,vcn33_1_bt;*S5gldo_vcn33_1_wifi ,vcn33_1_wifi;*S5gldo_vaux18,vaux18;w@Sw@kldo_vsram_others ,vsram_others; Skldo_vefuse,vefuse;Sldo_vxo22,vxo22;w@S!ldo_vrfck,vrfck;`Sldo_vrfck_1,vrfck;Sjldo_vbif28,vbif28;*S*kldo_vio28,vio28;*S2Zldo_vemc,vemc;,@ S2Zldo_vemc_1,vemc;&%S2ZFldo_vcn33_2_bt ,vcn33_2_bt;*S5gldo_vcn33_2_wifi ,vcn33_2_wifi;*S5gldo_va12,va12;OS ldo_va09,va09; 5SOldo_vrf18,vrf18;SPldo_vsram_md ,vsram_md; S*kldo_vufs,vufs;SGldo_vm18,vm18;Sldo_vbbck,vbbck;SOldo_vsram_proc1 ,vsram_proc1; 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disabledscp@10500000mediatek,mt8192-scp0Prpsramcfgl1tcm[mainokaymediatek/mt8192/scp.img'default(_cros-ecgoogle,cros-ec-rpmsg"cros-ec-rpmsgusb@11200000'mediatek,mt8192-xhcimediatek,mtk-xhci   > macippca6hostF)*"#]] 7+""R$sys_ckref_ckmcu_ckdma_ckxhci_ckK Y, fokayp-~.syscon@11210000mediatek,mt8192-audsyssyscon! f1mt8192-afe-pcmmediatek,mt8192-audio[/ audiosys+011111111111 1 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disabledclock-controller@11e01000mediatek,mt8192-imp_iic_wrap_wf?t-phy@11e40000.mediatek,mt8192-tphymediatek,generic-tphy-v2+fusb-phy@0"refN)usb-phy@700 "refN*dsi-phy@11e50000mediatek,mt8183-mipi-tx+ fN mipi_tx0_pll disabledOi2c@11f00000mediatek,mt8192-i2c !p[p@x maindma(+okaysdefaultAtouchscreen@10 defaultB hid-over-i2cY p>i2c@11f01000mediatek,mt8192-i2c !u[v@x maindma(+ disabledclock-controller@11f02000mediatek,mt8192-imp_iic_wrap_n f@clock-controller@11f10000mediatek,mt8192-msdc_topfCmmc@11f60000(mediatek,mt8192-mmcmediatek,mt8183-mmc [c8C CCCCC3sourcehclksource_cgsys_cgpclk_cgaxi_cgahb_cgokaydefaultstate_uhsDE + FG($,2mmc@11f70000(mediatek,mt8192-mmcmediatek,mt8183-mmc [g8C CCCCC3sourcehclksource_cgsys_cgpclk_cgaxi_cgahb_cgokaydefaultstate_uhsHI +  @JKIZg$uclock-controller@13fbf000mediatek,mt8192-mfgcfgfsyscon@14000000mediatek,mt8192-mmsyssysconf|LLLmutex@14001000mediatek,mt8192-disp-mutex[0 smi@14002000mediatek,mt8192-smi-common   apbsmigals0gals10 Mlarb@14003000mediatek,mt8192-smi-larb0M""apbsmi0 Plarb@14004000mediatek,mt8192-smi-larb@M""apbsmi0 Qovl@14005000mediatek,mt8192-disp-ovlP[NN0 LPovl@14006000mediatek,mt8192-disp-ovl-2l`[0 N"N L`rdma@140070004mediatek,mt8192-disp-rdmamediatek,mt8183-disp-rdmap[N0 Lpcolor@140090006mediatek,mt8192-disp-colormediatek,mt8173-disp-color[0 Lccorr@1400a000mediatek,mt8192-disp-ccorr[0  Laal@1400b0002mediatek,mt8192-disp-aalmediatek,mt8183-disp-aal[0 Lgamma@1400c0006mediatek,mt8192-disp-gammamediatek,mt8183-disp-gamma[0  Lpostmask@1400d000mediatek,mt8192-disp-postmask[0  Ldither@1400e0008mediatek,mt8192-disp-dithermediatek,mt8183-disp-dither[0  Ldsi@14010000mediatek,mt8183-dsi[  OenginedigitalhsFOdphy0  disabledportendpointovl@14014000mediatek,mt8192-disp-ovl-2l@[ 0 N#N!L@rdma@140150004mediatek,mt8192-disp-rdmamediatek,mt8183-disp-rdmaP[ 0 N%LPdpi@14016000mediatek,mt8192-dpi`[!+pixelenginepll disabledm4u@1401d000mediatek,mt8192-m4u<PQRSTUVWXYZ[\]^[bclk0 Nclock-controller@15020000mediatek,mt8192-imgsysflarb@1502e000mediatek,mt8192-smi-larb Mapbsmi0 Vclock-controller@15820000mediatek,mt8192-imgsys2flarb@1582e000mediatek,mt8192-smi-larb Mapbsmi0 Wlarb@1600d000mediatek,mt8192-smi-larbMapbsmi0Tclock-controller@1600f000mediatek,mt8192-vdecsys_socflarb@1602e000mediatek,mt8192-smi-larbMapbsmi0Sclock-controller@1602f000mediatek,mt8192-vdecsysfclock-controller@17000000mediatek,mt8192-vencsysflarb@17010000mediatek,mt8192-smi-larbMapbsmi0Uvcodec@17020000mediatek,mt8192-vcodec-enc XNNNNNNNNNNN[5_0 venc-set13Wclock-controller@1a000000mediatek,mt8192-camsysflarb@1a001000mediatek,mt8192-smi-larb Mapbsmi0Xlarb@1a002000mediatek,mt8192-smi-larb Mapbsmi0Ylarb@1a00f000mediatek,mt8192-smi-larbMapbsmi0Zlarb@1a010000mediatek,mt8192-smi-larbM  apbsmi0[larb@1a011000mediatek,mt8192-smi-larbM!!apbsmi0\clock-controller@1a04f000mediatek,mt8192-camsys_rawafclock-controller@1a06f000mediatek,mt8192-camsys_rawbf clock-controller@1a08f000mediatek,mt8192-camsys_rawcf!clock-controller@1b000000mediatek,mt8192-ipesysflarb@1b00f000mediatek,mt8192-smi-larbMapbsmi0 ^larb@1b10f000mediatek,mt8192-smi-larbMapbsmi0 ]clock-controller@1f000000mediatek,mt8192-mdpsysflarb@1f002000mediatek,mt8192-smi-larb Mapbsmi0 Rchosenserial0:115200n8memory@40000000memory@regulator-1v8-gregulator-fixed ,pp1800_ldo_g+;w@Sw@=-regulator-3v3-gregulator-fixed ,pp3300_g+;2ZS2Z=`-regulator-3v3-zregulator-fixed ,pp3300_ldo_z+;2ZS2Z=`regulator-3v3-uregulator-fixed ,pp3300_u+;2ZS2Z=->regulator-3v3-wlanregulator-fixed ,pp3300_wlan+;2ZS2ZdefaultaH [regulator-5v0-aregulator-fixed ,pp5000_a+;LK@SLK@=`.regulator-var-sysregulator-fixed ,ppvar_sys+`reserved-memory+fscp@50000000shared-dma-poolP`'wifi@c0000000restricted-dma-pool4 compatibleinterrupt-parent#address-cells#size-cellsmodelovl0ovl-2l0ovl-2l2rdma0rdma4serial0#clock-cellsclock-frequencyclock-output-namesphandledevice_typeregenable-methodcpu-idle-statesnext-level-cachecapacity-dmips-mhzcpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usinterruptsranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangesgpio-line-namespinmuxinput-enablebias-pull-updrive-strength-microampbias-disabledrive-strengthbias-pull-downoutput-highoutput-low#power-domain-cellsclocksclock-namesmediatek,infracfgassigned-clocksassigned-clock-parentsinterrupts-extendedmediatek,dmic-modemediatek,mic-type-0mediatek,mic-type-2regulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modesregulator-compatible#mbox-cellsstatus#pwm-cellsmediatek,pad-selectpinctrl-namespinctrl-0spi-max-frequencygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countlabelpower-roledata-roletry-power-rolekeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymapfunction-row-physmapcs-gpiosfirmware-namememory-regionmediatek,rpmsg-nameinterrupt-namesphyswakeup-sourcemediatek,syscon-wakeupvusb33-supplyvbus-supplyresetsreset-namesmediatek,apmixedsysmediatek,topckgenpower-domainsbus-rangeinterrupt-map-maskinterrupt-mapnum-lanesspi-rx-bus-widthspi-tx-bus-widthclock-divclock-stretch-nsvcc-supply#phy-cellspost-power-on-delay-mshid-descr-addrvdd-supplypinctrl-1vmmc-supplyvqmmc-supplycap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vsupports-cqecap-mmc-hw-resetmmc-hs400-enhanced-strobehs400-ds-delayno-sdiono-sdnon-removablecd-gpioscap-sd-highspeedsd-uhs-sdr50sd-uhs-sdr104no-mmcmboxesmediatek,gce-client-regmediatek,gce-eventsmediatek,larb-idmediatek,smiiommusmediatek,rdma-fifo-sizephy-namesmediatek,larbs#iommu-cellsmediatek,scpstdout-pathregulator-boot-onvin-supplyenable-active-highgpiono-map