8D( $mediatek,mt8192-evbmediatek,mt8192 +!7MediaTek MT8192 evaluation boardaliases=/soc/ovl@14005000B/soc/ovl@14006000J/soc/ovl@14014000R/soc/rdma@14007000X/soc/rdma@14015000^/soc/serial@11002000oscillator0 fixed-clockfsclk26m"oscillator1 fixed-clockfsclk32kcpus+cpu@0cpuarm,cortex-a55pscisec3@cpu@100cpuarm,cortex-a55pscisec3@ cpu@200cpuarm,cortex-a55pscisec3@ cpu@300cpuarm,cortex-a55pscisec3@ cpu@400cpuarm,cortex-a76pscisf cpu@500cpuarm,cortex-a76pscisf cpu@600cpuarm,cortex-a76pscisfcpu@700cpuarm,cortex-a76pscisfcpu-mapcluster0core0core1 core2 core3 cluster1core0 core1 core2core3l2-cache0cachel2-cache1cachel3-cachecacheidle-statespscicpu-sleep-larm,idle-state)7:J cpu-sleep-barm,idle-state)#:Jcluster-sleep-larm,idle-state)<:J\cluster-sleep-barm,idle-state)(:J pmu-a55arm,cortex-a55-pmu [pmu-a76arm,cortex-a76-pmu [psci arm,psci-1.0smctimerarm,armv8-timer @[   s]@soc+ simple-busfinterrupt-controller@c000000 arm,gic-v3m~    [ ppi-partitionsinterrupt-partition-0 interrupt-partition-1 syscon@10000000 mediatek,mt8192-topckgensysconfsyscon@10001000 mediatek,mt8192-infracfgsysconfsyscon@10003000mediatek,mt8192-pericfgsyscon0f&pinctrl@10005000mediatek,mt8192-pinctrlP]iocfg0iocfg_rmiocfg_bmiocfg_bliocfg_briocfg_lmiocfg_lbiocfg_rtiocfg_ltiocfg_tleint[msyscon@10006000)mediatek,mt8192-scpsyssysconsimple-mfd`power-controller!mediatek,mt8192-power-controller+(power-domain@0:/ audioaudio1audio2power-domain@1 connpower-domain@2 mfg+power-domain@3+power-domain@4power-domain@5power-domain@6power-domain@7power-domain@8power-domain@9 ( ! dispdisp-0disp-1disp-2disp-3+power-domain@10 ( ipeipe-0ipe-1ipe-2ipe-3power-domain@11  ispisp-0isp-1power-domain@12  isp2isp2-0isp2-1power-domain@13   mdpmdp-0power-domain@143  vencvenc-0power-domain@15 4 vdecvdec-0vdec-1vdec-2+power-domain@16 vdec2-0vdec2-1vdec2-2power-domain@17(  camcam-0cam-1cam-2cam-3+power-domain@18  cam_rawa-0power-domain@19   cam_rawb-0power-domain@20!  cam_rawc-0watchdog@10007000mediatek,mt8192-wdtp'syscon@1000c000"mediatek,mt8192-apmixedsyssysconf%timer@10017000,mediatek,mt8192-timermediatek,mt6765-timerp[ clk13mpwrap@10026000mediatek,mt6873-pwrap`pwrap[  spiwrap+;pmicmediatek,mt6359mmt6359codecregulatorsbuck_vs1Rvs1a 5y!buck_vgpu11Rvgpu11ay7 buck_vmodemRvmodemay*buck_vpuRvpuay7 buck_vcoreRvcoreay  buck_vs2Rvs2a 5yjbuck_vpaRvpaa y7,buck_vproc2Rvproc2ay7L buck_vproc1Rvproc1ay7L buck_vcore_sshub Rvcore_sshubay7buck_vgpu11_sshub Rvgpu11_sshubay7ldo_vaud18Rvaud18aw@yw@ldo_vsim1Rvsim1ay/M`ldo_vibrRvibraOy2Zldo_vrf12Rvrf12ay ldo_vusbRvusba-y-ldo_vsram_proc2 Rvsram_proc2a yLldo_vio18Rvio18ayldo_vcamioRvcamioayldo_vcn18Rvcn18aw@yw@ldo_vfe28Rvfe28a*y*xldo_vcn13Rvcn13a y ldo_vcn33_1_bt Rvcn33_1_bta*y5gldo_vcn33_1_wifi Rvcn33_1_wifia*y5gldo_vaux18Rvaux18aw@yw@ldo_vsram_others Rvsram_othersa yldo_vefuseRvefuseayldo_vxo22Rvxo22aw@y!ldo_vrfckRvrfcka`yldo_vrfck_1Rvrfckayjldo_vbif28Rvbif28a*y*ldo_vio28Rvio28a*y2Zldo_vemcRvemca,@ y2Zldo_vemc_1Rvemca&%y2Zldo_vcn33_2_bt Rvcn33_2_bta*y5gldo_vcn33_2_wifi Rvcn33_2_wifia*y5gldo_va12Rva12aOy ldo_va09Rva09a 5yOldo_vrf18Rvrf18ayPldo_vsram_md Rvsram_mda y*ldo_vufsRvufsayldo_vm18Rvm18ayldo_vbbckRvbbckayOldo_vsram_proc1 Rvsram_proc1a yLldo_vsim2Rvsim2ay/M`ldo_vsram_others_sshubRvsram_others_sshuba ymt6359rtcmediatek,mt6358-rtcspmi@10027000mediatek,mt6873-spmi p pmifspmimst8( pmif_sys_ckpmif_tmr_ckspmimst_clk_mux+;mailbox@10228000mediatek,mt8192-gce"@[ gce1clock-controller@10720000mediatek,mt8192-scp_adsprfserial@11002000*mediatek,mt8192-uartmediatek,mt6577-uart [m "  baudbusokayserial@11003000*mediatek,mt8192-uartmediatek,mt6577-uart0[n "  baudbus disabledclock-controller@11007000mediatek,mt8192-imp_iic_wrap_cpfspi@1100a000(mediatek,mt8192-spimediatek,mt6765-spi+[M parent-clksel-clkspi-clk disabledpwm@1100e000mediatek,mt8183-disp-pwm[!8 mainmm disabledspi@11010000(mediatek,mt8192-spimediatek,mt6765-spi+[M< parent-clksel-clkspi-clk disabledspi@11012000(mediatek,mt8192-spimediatek,mt6765-spi+ [M> parent-clksel-clkspi-clk disabledspi@11013000(mediatek,mt8192-spimediatek,mt6765-spi+0[M? parent-clksel-clkspi-clk disabledspi@11018000(mediatek,mt8192-spimediatek,mt6765-spi+[ML parent-clksel-clkspi-clk disabledspi@11019000(mediatek,mt8192-spimediatek,mt6765-spi+[MM parent-clksel-clkspi-clk disabledspi@1101d000(mediatek,mt8192-spimediatek,mt6765-spi+[Mm parent-clksel-clkspi-clk disabledspi@1101e000(mediatek,mt8192-spimediatek,mt6765-spi+[Mn parent-clksel-clkspi-clk disabledscp@10500000mediatek,mt8192-scp0Prpsramcfgl1tcm[ main disabledDusb@11200000'mediatek,mt8192-xhcimediatek,mtk-xhci   > macippc a host0#$+"#;]] 7%""R$ sys_ckref_ckmcu_ckdma_ckxhci_ck5 C& f disabledsyscon@11210000mediatek,mt8192-audsyssyscon! f)mt8192-afe-pcmmediatek,mt8192-audio[Z' aaudiosysm%())))))))))) ) ))))))))/:H/e0i+g,k;<=>?@ABCD7"u aud_afe_clkaud_dac_clkaud_dac_predis_clkaud_adc_clkaud_adda6_adc_clkaud_apll22m_clkaud_apll24m_clkaud_apll1_tuner_clkaud_apll2_tuner_clkaud_tdm_clkaud_tml_clkaud_nleaud_dac_hires_clkaud_adc_hires_clkaud_adc_hires_tmlaud_adda6_adc_hires_clkaud_3rd_dac_clkaud_3rd_dac_predis_clkaud_3rd_dac_tmlaud_3rd_dac_hires_clkaud_infra_clkaud_infra_26m_clktop_mux_audiotop_mux_audio_inttop_mainpll_d4_d4top_mux_aud_1top_apll1_cktop_mux_aud_2top_apll2_cktop_mux_aud_eng1top_apll1_d4top_mux_aud_eng2top_apll2_d4top_i2s0_m_seltop_i2s1_m_seltop_i2s2_m_seltop_i2s3_m_seltop_i2s4_m_seltop_i2s5_m_seltop_i2s6_m_seltop_i2s7_m_seltop_i2s8_m_seltop_i2s9_m_seltop_apll12_div0top_apll12_div1top_apll12_div2top_apll12_div3top_apll12_div4top_apll12_divbtop_apll12_div5top_apll12_div6top_apll12_div7top_apll12_div8top_apll12_div9top_mux_audio_htop_clk26m_clkpcie@11230000mediatek,mt8192-pciepci#  pcie-mac+0+'*j^\/ pl_250mtl_26mtl_96mtl_32kperi_26mtop_133m+);Q[8fm`****interrupt-controllerm*spi@11234000mediatek,mt8192-nor#@[:w]  spisfaxi+:;"+ disabledefuse@11c10000%mediatek,mt8192-efusemediatek,efuse+data1@1c0Xcalib@580hi2c@11cb0000mediatek,mt8192-i2c !s[s+x  maindma+ disabledclock-controller@11cb1000mediatek,mt8192-imp_iic_wrap_ef+i2c@11d00000mediatek,mt8192-i2c !v[w,x  maindma+ disabledi2c@11d01000mediatek,mt8192-i2c !w[x,x  maindma+ disabledi2c@11d02000mediatek,mt8192-i2c  !y[y,x  maindma+ disabledclock-controller@11d03000mediatek,mt8192-imp_iic_wrap_s0f,i2c@11d20000mediatek,mt8192-i2c !q[q-x  maindma+ disabledi2c@11d21000mediatek,mt8192-i2c !q[r-x  maindma+ disabledi2c@11d22000mediatek,mt8192-i2c  !s[t-x  maindma+ disabledclock-controller@11d23000 mediatek,mt8192-imp_iic_wrap_ws0f-i2c@11e00000mediatek,mt8192-i2c !u[u.x  maindma+ disabledclock-controller@11e01000mediatek,mt8192-imp_iic_wrap_wf.t-phy@11e40000.mediatek,mt8192-tphymediatek,generic-tphy-v2+fusb-phy@0" ref#usb-phy@700 " ref$dsi-phy@11e50000mediatek,mt8183-mipi-tx% f mipi_tx0_pll disabled4i2c@11f00000mediatek,mt8192-i2c !p[p/x  maindma+ disabledi2c@11f01000mediatek,mt8192-i2c !u[v/x  maindma+ disabledclock-controller@11f02000mediatek,mt8192-imp_iic_wrap_n f/clock-controller@11f10000mediatek,mt8192-msdc_topf0mmc@11f60000(mediatek,mt8192-mmcmediatek,mt8183-mmc [c80 000003 sourcehclksource_cgsys_cgpclk_cgaxi_cgahb_cg disabledmmc@11f70000(mediatek,mt8192-mmcmediatek,mt8183-mmc [g80 000003 sourcehclksource_cgsys_cgpclk_cgaxi_cgahb_cg disabledclock-controller@13fbf000mediatek,mt8192-mfgcfgfsyscon@14000000mediatek,mt8192-mmsyssysconf111mutex@14001000mediatek,mt8192-disp-mutex[( smi@14002000mediatek,mt8192-smi-common    apbsmigals0gals1( 2larb@14003000mediatek,mt8192-smi-larb0%2"" apbsmi( 5larb@14004000mediatek,mt8192-smi-larb@%2"" apbsmi( 6ovl@14005000mediatek,mt8192-disp-ovlP[233( 1Povl@14006000mediatek,mt8192-disp-ovl-2l`[( 23"3 1`rdma@140070004mediatek,mt8192-disp-rdmamediatek,mt8183-disp-rdmap[239( 1pcolor@140090006mediatek,mt8192-disp-colormediatek,mt8173-disp-color[( 1ccorr@1400a000mediatek,mt8192-disp-ccorr[(  1aal@1400b0002mediatek,mt8192-disp-aalmediatek,mt8183-disp-aal[( 1gamma@1400c0006mediatek,mt8192-disp-gammamediatek,mt8183-disp-gamma[(  1postmask@1400d000mediatek,mt8192-disp-postmask[(  1dither@1400e0008mediatek,mt8192-disp-dithermediatek,mt8183-disp-dither[(  1dsi@14010000mediatek,mt8183-dsi[  4 enginedigitalhs04Qdphy( Z disabledportendpointovl@14014000mediatek,mt8192-disp-ovl-2l@[ ( 23#3!1@rdma@140150004mediatek,mt8192-disp-rdmamediatek,mt8183-disp-rdmaP[ ( 23%91Pdpi@14016000mediatek,mt8192-dpi`[!% pixelenginepll disabledm4u@1401d000mediatek,mt8192-m4u<[56789:;<=>?@ABC[ bclk( j3clock-controller@15020000mediatek,mt8192-imgsysflarb@1502e000mediatek,mt8192-smi-larb %2 apbsmi( ;clock-controller@15820000mediatek,mt8192-imgsys2flarb@1582e000mediatek,mt8192-smi-larb %2 apbsmi( <larb@1600d000mediatek,mt8192-smi-larb%2 apbsmi(9clock-controller@1600f000mediatek,mt8192-vdecsys_socflarb@1602e000mediatek,mt8192-smi-larb%2 apbsmi(8clock-controller@1602f000mediatek,mt8192-vdecsysfclock-controller@17000000mediatek,mt8192-vencsysflarb@17010000mediatek,mt8192-smi-larb%2 apbsmi(:vcodec@17020000mediatek,mt8192-vcodec-enc X233333333333[5wD(  venc-set1+3;Wclock-controller@1a000000mediatek,mt8192-camsysflarb@1a001000mediatek,mt8192-smi-larb %2 apbsmi(=larb@1a002000mediatek,mt8192-smi-larb %2 apbsmi(>larb@1a00f000mediatek,mt8192-smi-larb%2 apbsmi(?larb@1a010000mediatek,mt8192-smi-larb%2   apbsmi(@larb@1a011000mediatek,mt8192-smi-larb%2!! apbsmi(Aclock-controller@1a04f000mediatek,mt8192-camsys_rawafclock-controller@1a06f000mediatek,mt8192-camsys_rawbf clock-controller@1a08f000mediatek,mt8192-camsys_rawcf!clock-controller@1b000000mediatek,mt8192-ipesysflarb@1b00f000mediatek,mt8192-smi-larb%2 apbsmi( Clarb@1b10f000mediatek,mt8192-smi-larb%2 apbsmi( Bclock-controller@1f000000mediatek,mt8192-mdpsysflarb@1f002000mediatek,mt8192-smi-larb %2 apbsmi( 7chosenserial0:921600n8memory@40000000memory@ compatibleinterrupt-parent#address-cells#size-cellsmodelovl0ovl-2l0ovl-2l2rdma0rdma4serial0#clock-cellsclock-frequencyclock-output-namesphandledevice_typeregenable-methodcpu-idle-statesnext-level-cachecapacity-dmips-mhzcpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usinterruptsranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-ranges#power-domain-cellsclocksclock-namesmediatek,infracfgassigned-clocksassigned-clock-parentsregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modes#mbox-cellsstatus#pwm-cellsinterrupts-extendedinterrupt-namesphyswakeup-sourcemediatek,syscon-wakeupresetsreset-namesmediatek,apmixedsysmediatek,topckgenpower-domainsbus-rangeinterrupt-map-maskinterrupt-mapclock-div#phy-cellsmboxesmediatek,gce-client-regmediatek,gce-eventsmediatek,larb-idmediatek,smiiommusmediatek,rdma-fifo-sizephy-namesmediatek,larbs#iommu-cellsmediatek,scpstdout-path