٬8(Dgoogle,tomato-rev4google,tomato-rev3google,tomatomediatek,mt8195 +7Acer Tomato (rev3 - 4) boardaliases=/soc/mailbox@10320000B/soc/mailbox@10330000G/soc/i2c@11e00000L/soc/i2c@11e01000Q/soc/i2c@11e02000V/soc/i2c@11e03000[/soc/i2c@11e04000`/soc/i2c@11d00000e/soc/i2c@11d02000j/soc/mmc@11230000o/soc/mmc@11240000t/soc/serial@11001100cpus+cpu@0|cpuarm,cortex-a55psciec3@4 cpu@100|cpuarm,cortex-a55psciec3@4 cpu@200|cpuarm,cortex-a55psciec3@4 cpu@300|cpuarm,cortex-a55psciec3@4 cpu@400|cpuarm,cortex-a78pscif cpu@500|cpuarm,cortex-a78pscifcpu@600|cpuarm,cortex-a78pscifcpu@700|cpuarm,cortex-a78pscifcpu-mapcluster0core0 core1 core2 core3 cluster1core0 core1 core2 core3 idle-states pscicpu-off-larm,idle-state1B2S_cDcpu-off-barm,idle-state1B-Sccluster-off-larm,idle-state1B7ScHcluster-off-barm,idle-state1B2Scl2-cache0cachel2-cache1cachel3-cachecachedsu-pmu arm,dsu-pmut  dmic-codec dmic-codec2mt8195-sound disabledoscillator-26m fixed-clockclk26m(oscillator-32k fixed-clockclk32kperformance-controller@11bc10mediatek,cpufreq-hw  0 pmu-a55arm,cortex-a55-pmu tpmu-a78arm,cortex-a78-pmu tpsci arm,psci-1.0smctimerarm,armv8-timer @t   soc+ simple-businterrupt-controller@c000000 arm,gic-v3  #   t ppi-partitionsinterrupt-partition-08 interrupt-partition-18 syscon@10000000 mediatek,mt8195-topckgensysconsyscon@10001000.mediatek,mt8195-infracfg_aosysconsimple-mfdAsyscon@10003000mediatek,mt8195-pericfgsyscon02pinctrl@10005000mediatek,mt8195-pinctrlPBNiocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleintXht#tdefault>I2S_SPKR_MCLKI2S_SPKR_DATAINI2S_SPKR_LRCKI2S_SPKR_BCLKEC_AP_INT_ODLAP_FLASH_WP_LTCHPAD_INT_ODLEDP_HPD_1V8AP_I2C_CAM_SDAAP_I2C_CAM_SCLAP_I2C_TCHPAD_SDA_1V8AP_I2C_TCHPAD_SCL_1V8AP_I2C_AUD_SDAAP_I2C_AUD_SCLAP_I2C_TPM_SDA_1V8AP_I2C_TPM_SCL_1V8AP_I2C_TCHSCR_SDA_1V8AP_I2C_TCHSCR_SCL_1V8EC_AP_HPD_ODPCIE_NVME_RST_LPCIE_NVME_CLKREQ_ODLPCIE_RST_1V8_LPCIE_CLKREQ_1V8_ODLPCIE_WAKE_1V8_ODLCLK_24M_CAM0CAM1_SEN_ENAP_I2C_PWR_SCL_1V8AP_I2C_PWR_SDA_1V8AP_I2C_MISC_SCLAP_I2C_MISC_SDAEN_PP5000_HDMI_XAP_HDMITX_HTPLGAP_HDMITX_SCL_1V8AP_HDMITX_SDA_1V8AP_RTC_CLK32KAP_EC_WATCHDOG_LSRCLKENA0SRCLKENA1PWRAP_SPI0_CS_LPWRAP_SPI0_CKPWRAP_SPI0_MOSIPWRAP_SPI0_MISOSPMI_SCLSPMI_SDAI2S_HP_DATAINI2S_HP_MCLKI2S_HP_BCKI2S_HP_LRCKI2S_HP_DATAOUTSD_CD_ODLEN_PP3300_DISP_XTCHSCR_RST_1V8_LTCHSCR_REPORT_DISABLEEN_PP3300_WLAN_XBT_KILL_1V8_LI2S_SPKR_DATAOUTWIFI_KILL_1V8_LBEEP_ONSCP_I2C_SENSOR_SCL_1V8SCP_I2C_SENSOR_SDA_1V8AUD_CLK_MOSIAUD_SYNC_MOSIAUD_DAT_MOSI0AUD_DAT_MOSI1AUD_DAT_MISO0AUD_DAT_MISO1AUD_DAT_MISO2SCP_VREQ_VAOAP_SPI_GSC_TPM_CLKAP_SPI_GSC_TPM_MOSIAP_SPI_GSC_TPM_CS_LAP_SPI_GSC_TPM_MISOEN_PP1000_CAM_XAP_EDP_BKLTENUSB3_HUB_RST_LWLAN_ALERT_ODLEC_IN_RW_ODLGSC_AP_INT_ODLHP_INT_ODLCAM0_RST_LCAM1_RST_LTCHSCR_INT_1V8_LCAM1_DET_LRST_ALC1011_LBL_PWM_1V8UART_AP_TX_DBG_RXUART_DBG_TX_AP_RXEN_SPKRAP_EC_WARM_RST_REQUART_SCP_TX_DBGCON_RXUART_DBGCON_TX_SCP_RXKPCOL0MT6315_GPU_INTMT6315_PROC_BC_INTSD_CMDSD_CLKSD_DAT0SD_DAT1SD_DAT2SD_DAT3EMMC_DAT7EMMC_DAT6EMMC_DAT5EMMC_DAT4EMMC_RSTBEMMC_CMDEMMC_CLKEMMC_DAT3EMMC_DAT2EMMC_DAT1EMMC_DAT0EMMC_DSLMT6360_INT_ODLSCP_JTAG0_TRSTNAP_SPI_EC_CS_LAP_SPI_EC_CLKAP_SPI_EC_MOSIAP_SPI_EC_MISOSCP_JTAG0_TMSSCP_JTAG0_TCKSCP_JTAG0_TDOSCP_JTAG0_TDIAP_SPI_FLASH_CS_LAP_SPI_FLASH_CLKAP_SPI_FLASH_MOSIAP_SPI_FLASH_MISOcr50-irq-default-pinsLpins-gsc-ap-int-odlXcros-ec-irq-default-pins/pins-ec-ap-int-odlei2c0-default-pinsFpins-bus i2c1-default-pinsGpins-bus  i2c2-default-pinsJpins-bus  i2c3-default-pinsKpins-busi2c4-default-pinsMpins-busi2c5-default-pinsBpins-busi2c7-default-pinsCpins-busmmc0-default-pins5pins-cmd-dat$~}|{wvutyepins-clkz!fpins-rstxemmc0-uhs-pins6pins-cmd-dat$~}|{wvutyepins-clkz!fpins-ds!fpins-rstxemmc1-detect-pins:pins-insert6mmc1-default-pins9pins-cmd-datnpqrsepins-clko!fnor-default-pins@pins-ck-io !pins-cspio-default-pinspins-wifi-enable:0pins-low-power-pd,./0ABCD!pins-low-power-pupd<MNOPSUZ[]^_`hik!epins-low-power-hdmi-disable !"#!pins-low-power-pcie0-disable !scp-default-pins'pins-vreqLspi0-default-pins.pins-cs-mosi-clk pins-miso!subpmic-default-pinsDpins-subpmic-int-ntrackpad-default-pinsHpins-int-ntouchscreen-default-pinsNpins-int-n\epins-rst80pins-report-sw9<syscon@10006000)mediatek,mt8195-scpsyssysconsimple-mfd`power-controller!mediatek,mt8195-power-controller+G*power-domain@8+Gpower-domain@9 [bmfgn+Gpower-domain@10 Gpower-domain@11 Gpower-domain@12 Gpower-domain@13 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W.infra-iommu@10315000mediatek,mt8195-iommu-infra1PPPtmailbox@10320000mediatek,mt8195-gce2@t[tmailbox@10330000mediatek,mt8195-gce3@t[scp@10500000mediatek,mt8195-scp0PrpNsramcfgl1tcmtokaymediatek/mt8195/scp.img&default'cros-ec-rpmsggoogle,cros-ec-rpmsgcros-ec-rpmsgclock-controller@10720000mediatek,mt8195-scp_adspr)dsp@10803000mediatek,mt8195-dsp 0 Ncfgsram,[X(n)#Kbadsp_selclk26m_ckaudio_local_busmainpll_d7_d2scp_adsp_audiodspaudio_h*rxtx+, disabledmailbox@10816000mediatek,mt8195-adsp-mbox`t+mailbox@10817000mediatek,mt8195-adsp-mboxpt,mt8195-afe-pcm@10890000mediatek,mt8195-audio*t6- audiosys[(g"#neabcd2)bclk26mapll1_ckapll2_ckapll12_div0apll12_div1apll12_div2apll12_div3apll12_div9a1sys_hp_selaud_intbus_selaudio_h_selaudio_local_bus_seldptx_m_seli2so1_m_seli2so2_m_seli2si1_m_seli2si2_m_selinfra_ao_audio_26m_bscp_adsp_audiodsp disabledserial@11001100*mediatek,mt8195-uartmediatek,mt6577-uartt [( bbaudbusokayserial@11001200*mediatek,mt8195-uartmediatek,mt6577-uartt [( bbaudbus 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compatibleinterrupt-parent#address-cells#size-cellsmodelgce0gce1i2c0i2c1i2c2i2c3i2c4i2c5i2c7mmc0mmc1serial0device_typeregenable-methodperformance-domainsclock-frequencycapacity-dmips-mhzcpu-idle-statesnext-level-cache#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usinterruptscpusnum-channelswakeup-delay-msmediatek,platformstatus#clock-cellsclock-output-names#performance-domain-cellsranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangesmediatek,rsel-resistance-in-si-unitpinctrl-namespinctrl-0gpio-line-namespinmuxinput-enablebias-pull-upbias-disabledrive-strength-microampdrive-strengthbias-pull-downoutput-highoutput-low#power-domain-cellsclocksclock-namesmediatek,infracfgmediatek,disable-extrstassigned-clocksassigned-clock-parentsinterrupts-extendedregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modesregulator-compatible#iommu-cells#mbox-cellsfirmware-namememory-regionmediatek,rpmsg-namepower-domainsmbox-namesmboxesmediatek,topckgenresetsreset-names#io-channel-cellsmediatek,pad-selectspi-max-frequencygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countpower-roledata-roletry-power-rolekeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymapfunction-row-physmapphysmediatek,syscon-wakeupwakeup-sourcevusb33-supplyvbus-supplybus-widthcap-mmc-highspeedcap-mmc-hw-reseths400-ds-delaymmc-hs200-1_8vmmc-hs400-1_8vno-sdiono-sdnon-removablepinctrl-1vmmc-supplyvqmmc-supplycap-sd-highspeedcd-gpiosno-mmcsd-uhs-sdr50sd-uhs-sdr104usb2-lpm-disablespi-rx-bus-widthspi-tx-bus-widthbits#phy-cellsclock-divinterrupt-namesi2c-scl-internal-delay-nsvcc-supplyhid-descr-addrpost-power-on-delay-msvdd-supplynvmem-cellsnvmem-cell-namesmediatek,smimediatek,larb-idmediatek,larbsiommusmediatek,gce-client-regmediatek,gce-eventsstdout-pathregulator-boot-onvin-supplyenable-active-highno-map