58(}%mediatek,mt8195-demomediatek,mt8195 +7MediaTek MT8195 demo boardaliases=/soc/mailbox@10320000B/soc/mailbox@10330000G/soc/serial@11001100cpus+cpu@0Ocpuarm,cortex-a55[_pscimec3@4 cpu@100Ocpuarm,cortex-a55[_pscimec3@4 cpu@200Ocpuarm,cortex-a55[_pscimec3@4 cpu@300Ocpuarm,cortex-a55[_pscimec3@4 cpu@400Ocpuarm,cortex-a78[_pscimf cpu@500Ocpuarm,cortex-a78[_pscimfcpu@600Ocpuarm,cortex-a78[_pscimfcpu@700Ocpuarm,cortex-a78[_pscimfcpu-mapcluster0core0 core1 core2 core3 cluster1core0 core1core2core3idle-statespscicpu-off-larm,idle-state2&_6Dcpu-off-barm,idle-state-&6cluster-off-larm,idle-state7&6Hcluster-off-barm,idle-state2&6l2-cache0cachel2-cache1cachel3-cachecachedsu-pmu arm,dsu-pmuG R dmic-codec dmic-codecWd2mt8195-soundt disabledoscillator-26m fixed-clockclk26m%oscillator-32k fixed-clockclk32kperformance-controller@11bc10mediatek,cpufreq-hw [ 0 pmu-a55arm,cortex-a55-pmu Gpmu-a78arm,cortex-a78-pmu Gpsci arm,psci-1.0fsmctimerarm,armv8-timer @G   soc+ simple-businterrupt-controller@c000000 arm,gic-v3  [   G ppi-partitionsinterrupt-partition-0 interrupt-partition-1 syscon@10000000 mediatek,mt8195-topckgensyscon[syscon@10001000.mediatek,mt8195-infracfg_aosysconsimple-mfd[syscon@10003000mediatek,mt8195-pericfgsyscon[0/pinctrl@10005000mediatek,mt8195-pinctrl[PB!iocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleint+;GGgpio-keys-pinswpinsSjZi2c6-pins>pinsSgmmc0-default-pins2pins-clkSztfpins-cmd-dat$S~}|{wvutyZtgepins-rstSxtgemmc0-uhs-pins3pins-clkSztfpins-cmd-dat$S~}|{wvutyZtgepins-dsStfpins-rstSxtgemmc1-default-pins6pins-clkSotfpins-cmd-datSnpqrsZtgepins-insertSgmmc1-uhs-pins7pins-clkSotfpins-cmd-datSnpqrsZtgeuart0-pins+pinsSbcuart1-pins,pinsSfgsyscon@10006000)mediatek,mt8195-scpsyssysconsimple-mfd[`power-controller!mediatek,mt8195-power-controller+'power-domain@8[+power-domain@9[ mfg+power-domain@10[ power-domain@11[ power-domain@12[ power-domain@13[ power-domain@14[power-domain@15[ @AK   vppsysvppsys1vppsys2vppsys3vppsys4vppsys5vppsys6vppsys7vppsys0-0vppsys0-1vppsys0-2vppsys0-3vppsys0-4vppsys0-5vppsys0-6vppsys0-7vppsys0-8vppsys0-9vppsys0-10vppsys0-11vppsys0-12vppsys0-13vppsys0-14vppsys0-15vppsys0-16vppsys0-17vppsys0-18+power-domain@24[vdec1-0power-domain@27[power-domain@16[8$%&'()Dvdosys0vdosys0-0vdosys0-1vdosys0-2vdosys0-3vdosys0-4vdosys0-5+power-domain@17[vppsys1vppsys1-0vppsys1-1power-domain@22[ $wepsys-0wepsys-1wepsys-2wepsys-3power-domain@23[vdec0-0power-domain@25[vdec2-0power-domain@26[power-domain@18[   &vdosys1vdosys1-0vdosys1-1vdosys1-2+power-domain@19[power-domain@20[power-domain@21[Qhdmi_txpower-domain@28[!!  img-0img-1+power-domain@29[power-domain@30[!"ipeipe-0ipe-1power-domain@31[(#####cam-0cam-1cam-2cam-3cam-4+power-domain@32[ power-domain@33[!power-domain@34["power-domain@0[power-domain@1[power-domain@2[power-domain@3[power-domain@4[57csi_rx_topcsi_rx_top1power-domain@5[$ etherpower-domain@6[Xn adspadsp1+power-domain@7[ g"n2audioaudio1audio2audio3watchdog@10007000(mediatek,mt8195-wdtmediatek,mt6589-wdt[p*syscon@1000c000"mediatek,mt8195-apmixedsyssyscon[timer@10017000,mediatek,mt8195-timermediatek,mt6765-timer[pG upwrap@10024000mediatek,mt8195-pwrapsyscon[@!pwrapG spiwrap$pmicmediatek,mt6359  mt6359codecregulatorsbuck_vs1vs1- 5E!]ybuck_vgpu11vgpu11-E7] ybuck_vmodemvmodem-E*]buck_vpuvpu-E7] ybuck_vcorevcore-E ] ybuck_vs2vs2- 5Ej]ybuck_vpavpa- E7],buck_vproc2vproc2-E7L] ybuck_vproc1vproc1-E7L] ybuck_vcore_sshub vcore_sshub-E7buck_vgpu11_sshub vgpu11_sshub-E7ldo_vaud18vaud18-w@Ew@]ldo_vsim1vsim1-E/M`ldo_vibrvibr-OE2Zldo_vrf12vrf12-E yldo_vusbvusb--E-]y0ldo_vsram_proc2 vsram_proc2- EL]yldo_vio18vio18-E]yldo_vcamiovcamio-Eldo_vcn18vcn18-w@Ew@]ldo_vfe28vfe28-*E*]xldo_vcn13vcn13- E ldo_vcn33_1_bt vcn33_1_bt-*E5gldo_vcn33_1_wifi vcn33_1_wifi-*E5gldo_vaux18vaux18-w@Ew@]yldo_vsram_others vsram_others- E]yldo_vefusevefuse-Eldo_vxo22vxo22-w@E!yldo_vrfckvrfck-`Eldo_vrfck_1vrfck-Ejldo_vbif28vbif28-*E*]ldo_vio28vio28-*E2Zyldo_vemcvemc-,@ E2Zldo_vemc_1vemc-&%E2Z4ldo_vcn33_2_bt vcn33_2_bt-*E5gldo_vcn33_2_wifi vcn33_2_wifi-*E5gldo_va12va12-OE yldo_va09va09- 5EOldo_vrf18vrf18-EPldo_vsram_md vsram_md- E*]yldo_vufsvufs-E5ldo_vm18vm18-Eyldo_vbbckvbbck-EOyldo_vsram_proc1 vsram_proc1- EL]yldo_vsim2vsim2-E/M`ldo_vsram_others_sshubvsram_others_sshub- Emt6359rtcmediatek,mt6358-rtcspmi@10027000mediatek,mt8195-spmi [p !pmifspmimstE(pmif_sys_ckpmif_tmr_ckspmimst_clk_mux$infra-iommu@10315000mediatek,mt8195-iommu-infra[1PPPGmailbox@10320000mediatek,mt8195-gce[2@Gfmailbox@10330000mediatek,mt8195-gce[3@Gscp@10500000mediatek,mt8195-scp0[Prp!sramcfgl1tcmG disabledclock-controller@10720000mediatek,mt8195-scp_adsp[r&dsp@10803000mediatek,mt8195-dsp [0 !cfgsram,X%n&#Kadsp_selclk26m_ckaudio_local_busmainpll_d7_d2scp_adsp_audiodspaudio_h'rxtx() disabledmailbox@10816000mediatek,mt8195-adsp-mbox[`G(mailbox@10817000mediatek,mt8195-adsp-mbox[pG)mt8195-afe-pcm@10890000mediatek,mt8195-audio['G6*  audiosys%g"#neabcd2&clk26mapll1_ckapll2_ckapll12_div0apll12_div1apll12_div2apll12_div3apll12_div9a1sys_hp_selaud_intbus_selaudio_h_selaudio_local_bus_seldptx_m_seli2so1_m_seli2so2_m_seli2si1_m_seli2si2_m_selinfra_ao_audio_26m_bscp_adsp_audiodsp disabledserial@11001100*mediatek,mt8195-uartmediatek,mt6577-uart[G % baudbusokaydefault&+serial@11001200*mediatek,mt8195-uartmediatek,mt6577-uart[G % baudbusokaydefault&,serial@11001300*mediatek,mt8195-uartmediatek,mt6577-uart[G % baudbus disabledserial@11001400*mediatek,mt8195-uartmediatek,mt6577-uart[G % baudbus disabledserial@11001500*mediatek,mt8195-uartmediatek,mt6577-uart[G % baudbus disabledserial@11001600*mediatek,mt8195-uartmediatek,mt6577-uart[G % baudbus disabledauxadc@11002000.mediatek,mt8195-auxadcmediatek,mt8173-auxadc[ main0 disabledsyscon@11003000"mediatek,mt8195-pericfg_aosyscon[0$spi@1100a000(mediatek,mt8195-spimediatek,mt6765-spi+[Gparent-clksel-clkspi-clk disabledspi@11010000(mediatek,mt8195-spimediatek,mt6765-spi+[G3parent-clksel-clkspi-clk disabledspi@11012000(mediatek,mt8195-spimediatek,mt6765-spi+[ G4parent-clksel-clkspi-clk disabledspi@11013000(mediatek,mt8195-spimediatek,mt6765-spi+[0G5parent-clksel-clkspi-clk disabledspi@11018000(mediatek,mt8195-spimediatek,mt6765-spi+[G<parent-clksel-clkspi-clk disabledspi@11019000(mediatek,mt8195-spimediatek,mt6765-spi+[G=parent-clksel-clkspi-clk disabledspi@1101d000mediatek,mt8195-spi-slave[GRspi disabledspi@1101e000mediatek,mt8195-spi-slave[GSspi disabledusb@11200000'mediatek,mt8195-xhcimediatek,mtk-xhci [  > !macippcGB-.,-$/%B$sys_ckref_ckmcu_ckdma_ckxhci_ck G/g^okayl0z1mmc@11230000(mediatek,mt8195-mmcmediatek,mt8183-mmc [#Gsourcehclksource_cgokaydefaultstate_uhs&23 L45mmc@11240000(mediatek,mt8195-mmcmediatek,mt8183-mmc [$G$sourcehclksource_cgokaydefaultstate_uhs&67 - 6GT89mmc@11250000(mediatek,mt8195-mmcmediatek,mt8183-mmc [%G Isourcehclksource_cg  disabledusb@11290000'mediatek,mt8195-xhcimediatek,mtk-xhci [))> !macippcGB:./$$%$$sys_ckref_ckmcu_ckdma_ckxhci_ck G/h^okayl0usb@112a0000'mediatek,mt8195-xhcimediatek,mtk-xhci [**> !macippcGB;01 $%%$$sys_ckref_ckmcu_ckdma_ckxhci_ck G/i^okayl0usb@112b0000'mediatek,mt8195-xhcimediatek,mtk-xhci [++> !macippcGB<23 $%%$ $sys_ckref_ckmcu_ckdma_ckxhci_ck G/j^okayl0spi@1132c000(mediatek,mt8195-normediatek,mt8173-nor[2G9o$$ spisfaxi+ disabledefuse@11c10000%mediatek,mt8195-efusemediatek,efuse[+usb3-tx-imp@184,1[bFusb3-rx-imp@184,2[bEusb3-intr@185[bDusb3-tx-imp@186,1[bCusb3-rx-imp@186,2[bBusb3-intr@187[bAusb2-intr-p0@188,1[busb2-intr-p1@188,2[busb2-intr-p2@189,1[busb2-intr-p3@189,2[bt-phy@11c40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+okayusb-phy@0[refg;t-phy@11c50000.mediatek,mt8195-tphymediatek,generic-tphy-v3+okayusb-phy@0[refg<i2c@11d00000(mediatek,mt8195-i2cmediatek,mt8192-i2c ["Gr=; maindma+ disabledi2c@11d01000(mediatek,mt8195-i2cmediatek,mt8192-i2c ["Gr=; maindma+okay&>defaultpmic@34mediatek,mt6360[4  e|IRQBchargermediatek,mt6360-chg@usb-otg-vbus-regulator usb-otg-vbus usb-otg-vbus-C(EX1regulatormediatek,mt6360-regulator?buck1BUCK1 mt6360,buck1-E  ybuck2BUCK2 mt6360,buck2-E  y?ldo1LDO1 mt6360,ldo1-OE6ldo2LDO2 mt6360,ldo2-OE6ldo3LDO3 mt6360,ldo3-OE69ldo5LDO5 mt6360,ldo5-)2E68ldo6LDO6 mt6360,ldo6- E ldo7LDO7 mt6360,ldo7- E yi2c@11d02000(mediatek,mt8195-i2cmediatek,mt8192-i2c [ "Gr=; maindma+ disabledclock-controller@11d03000mediatek,mt8195-imp_iic_wrap_s[0=i2c@11e00000(mediatek,mt8195-i2cmediatek,mt8192-i2c ["Gr@; maindma+ disabledi2c@11e01000(mediatek,mt8195-i2cmediatek,mt8192-i2c ["Gr@; maindma+ disabledi2c@11e02000(mediatek,mt8195-i2cmediatek,mt8192-i2c [ "Gr@; maindma+ disabledi2c@11e03000(mediatek,mt8195-i2cmediatek,mt8192-i2c [0"Gr@; maindma+ disabledi2c@11e04000(mediatek,mt8195-i2cmediatek,mt8192-i2c [@"Gr@; maindma+ disabledclock-controller@11e05000mediatek,mt8195-imp_iic_wrap_w[P@t-phy@11e30000.mediatek,mt8195-tphymediatek,generic-tphy-v3+okayusb-phy@0[ % refda_refg:usb-phy@700[ refda_ref ABCintrrx_imptx_impgt-phy@11e40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+okayusb-phy@0[ % refda_refg-usb-phy@700[ refda_ref DEFintrrx_imptx_impg.ufs-phy@11fa0000.mediatek,mt8195-ufsphymediatek,mt8183-ufsphy[%% uniprompg disabledclock-controller@13fbf000mediatek,mt8195-mfgcfg[clock-controller@14000000mediatek,mt8195-vppsys0[smi@14010000mediatek,mt8195-smi-sub-common[apbsmigals0G'Hsmi@14011000mediatek,mt8195-smi-sub-common[apbsmigals0G'dsmi@14012000mediatek,mt8195-smi-common-vpp[  apbsmigals0gals1'Glarb@14013000mediatek,mt8195-smi-larb[0Hapbsmi'Kiommu@14018000mediatek,mt8195-iommu-vpp[8IJKLMNOPQRSTUVGRbclk'clock-controller@14e00000mediatek,mt8195-wpesys[clock-controller@14e02000mediatek,mt8195-wpesys_vpp0[ clock-controller@14e03000mediatek,mt8195-wpesys_vpp1[0larb@14e04000mediatek,mt8195-smi-larb[@Wapbsmi'llarb@14e05000mediatek,mt8195-smi-larb[PG apbsmigals'Mclock-controller@14f00000mediatek,mt8195-vppsys1[larb@14f02000mediatek,mt8195-smi-larb[ W apbsmigals'klarb@14f03000mediatek,mt8195-smi-larb[0H apbsmigals'Lclock-controller@15000000mediatek,mt8195-imgsys[!larb@15001000mediatek,mt8195-smi-larb[ X!!!  apbsmigals'msmi@15002000mediatek,mt8195-smi-sub-common[ !!apbsmigals0G'[smi@15003000mediatek,mt8195-smi-sub-common[0!!! apbsmigals0W'Xclock-controller@15110000 mediatek,mt8195-imgsys1_dip_top[Ylarb@15120000mediatek,mt8195-smi-larb[ X!Yapbsmi'nclock-controller@15130000mediatek,mt8195-imgsys1_dip_nr[clock-controller@15220000mediatek,mt8195-imgsys1_wpe["Zlarb@15230000mediatek,mt8195-smi-larb[# X!Zapbsmi'oclock-controller@15330000mediatek,mt8195-ipesys[3"larb@15340000mediatek,mt8195-smi-larb[4 [""apbsmi'Nclock-controller@16000000mediatek,mt8195-camsys[#larb@16001000mediatek,mt8195-smi-larb[ \### apbsmigals'plarb@16002000mediatek,mt8195-smi-larb[ ]##apbsmi'Osmi@16004000mediatek,mt8195-smi-sub-common[@###apbsmigals0W'\smi@16005000mediatek,mt8195-smi-sub-common[P##apbsmigals0G']larb@16012000mediatek,mt8195-smi-larb[ ]^^apbsmi' Plarb@16013000mediatek,mt8195-smi-larb[0\__apbsmi' qlarb@16014000mediatek,mt8195-smi-larb[@]``apbsmi'!Vlarb@16015000mediatek,mt8195-smi-larb[P\aaapbsmi'!vclock-controller@1604f000mediatek,mt8195-camsys_rawa[^clock-controller@1606f000mediatek,mt8195-camsys_yuva[_clock-controller@1608f000mediatek,mt8195-camsys_rawb[`clock-controller@160af000mediatek,mt8195-camsys_yuvb[ aclock-controller@16140000mediatek,mt8195-camsys_mraw[blarb@16141000mediatek,mt8195-smi-larb[\#b# apbsmigals'"ularb@16142000mediatek,mt8195-smi-larb[ ]bbapbsmi'"Uclock-controller@17200000mediatek,mt8195-ccusys[ clarb@17201000mediatek,mt8195-smi-larb[ ]ccapbsmi'Qlarb@1800d000mediatek,mt8195-smi-larb[Wapbsmi'tlarb@1800e000mediatek,mt8195-smi-larb[dapbsmi'Tclock-controller@1800f000mediatek,mt8195-vdecsys_soc[larb@1802e000mediatek,mt8195-smi-larb[Wapbsmi'sclock-controller@1802f000mediatek,mt8195-vdecsys[larb@1803e000mediatek,mt8195-smi-larb[dapbsmi'Sclock-controller@1803f000mediatek,mt8195-vdecsys_core1[clock-controller@190f3000mediatek,mt8195-apusys_pll[0clock-controller@1a000000mediatek,mt8195-vencsys[elarb@1a010000mediatek,mt8195-smi-larb[Weeapbsmi'rclock-controller@1b000000mediatek,mt8195-vencsys_core1[gsyscon@1c01a000mediatek,mt8195-mmsyssyscon[ flarb@1b010000mediatek,mt8195-smi-larb[Ggg  apbsmigals'Rovl@1c0000002mediatek,mt8195-disp-ovlmediatek,mt8183-disp-ovl[G|'hfrdma@1c002000mediatek,mt8195-disp-rdma[ G~'hf color@1c0030006mediatek,mt8195-disp-colormediatek,mt8173-disp-color[0G'f0ccorr@1c0040006mediatek,mt8195-disp-ccorrmediatek,mt8192-disp-ccorr[@G'f@aal@1c0050002mediatek,mt8195-disp-aalmediatek,mt8183-disp-aal[PG'fPgamma@1c0060006mediatek,mt8195-disp-gammamediatek,mt8183-disp-gamma[`G'f`dither@1c0070008mediatek,mt8195-disp-dithermediatek,mt8183-disp-dither[pG' fpdsc@1c009000mediatek,mt8195-disp-dsc[G'fmerge@1c014000mediatek,mt8195-disp-merge[@G'f@mutex@1c016000mediatek,mt8195-disp-mutex[`G'3Ularb@1c018000mediatek,mt8195-smi-larb[W((  apbsmigals'ilarb@1c019000mediatek,mt8195-smi-larb[G(  apbsmigals'Isyscon@1c100000mediatek,mt8195-mmsyssyscon[ smi@1c01b000mediatek,mt8195-smi-common-vdo[ %&)$apbsmigals0gals1'Wiommu@1c01f000mediatek,mt8195-iommu-vdo[8ijklmnopqrstuvG'bclk'hlarb@1c102000mediatek,mt8195-smi-larb[ W  apbsmigals'jlarb@1c103000mediatek,mt8195-smi-larb[0G    apbsmigals'JchosenGserial0:921600n8firmwareopteelinaro,optee-tzfsmcgpio-keys gpio-keysdefault&wkey-0 0j Svolume_upYs^dmemory@40000000Omemory[@reserved-memory+secmon@54600000v[T` optee@43200000v[C  compatibleinterrupt-parent#address-cells#size-cellsmodelgce0gce1serial0device_typeregenable-methodperformance-domainsclock-frequencycapacity-dmips-mhzcpu-idle-statesnext-level-cache#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usinterruptscpusnum-channelswakeup-delay-msmediatek,platformstatus#clock-cellsclock-output-names#performance-domain-cellsranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxinput-enablebias-pull-updrive-strengthbias-pull-down#power-domain-cellsclocksclock-namesmediatek,infracfgmediatek,disable-extrstassigned-clocksassigned-clock-parentsinterrupts-extendedregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modes#iommu-cells#mbox-cellspower-domainsmbox-namesmboxesmediatek,topckgenresetsreset-namespinctrl-namespinctrl-0#io-channel-cellsphysmediatek,syscon-wakeupwakeup-sourcevusb33-supplyvbus-supplypinctrl-1bus-widthmax-frequencycap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vcap-mmc-hw-resetno-sdiono-sdhs400-ds-delayvmmc-supplyvqmmc-supplynon-removablecd-gpioscap-sd-highspeedsd-uhs-sdr50sd-uhs-sdr104bits#phy-cellsclock-divinterrupt-namesrichtek,vinovp-microvoltregulator-compatibleLDO_VIN3-supplynvmem-cellsnvmem-cell-namesmediatek,smimediatek,larb-idmediatek,larbsiommusmediatek,gce-client-regmediatek,gce-eventsstdout-pathlabellinux,codedebounce-intervalno-map