|w8v8(?v&firefly,roc-rk3308-ccrockchip,rk3308 +7Firefly ROC-RK3308-CC boardaliases=/i2c@ff040000B/i2c@ff050000G/i2c@ff060000L/i2c@ff070000Q/serial@ff0a0000Y/serial@ff0b0000a/serial@ff0c0000i/serial@ff0d0000q/serial@ff0e0000y/spi@ff120000~/spi@ff130000/spi@ff140000/mmc@ff480000/mmc@ff490000cpus+cpu@0cpuarm,cortex-a35psciZ cpu@1cpuarm,cortex-a35psci cpu@2cpuarm,cortex-a35psci cpu@3cpuarm,cortex-a35psci idle-states(pscicpu-sleeparm,idle-state5F]xn~ l2-cachecache opp-table-0operating-points-v2 opp-408000000Q ~~r`@opp-600000000#F ~~r`@opp-8160000000, r`@opp-1008000000< **r`@arm-pmuarm,cortex-a35-pmu0STUV external-mac-clock fixed-clock mac_clkin psci arm,psci-1.0smctimerarm,armv8-timer0   xin24m fixed-clock n6xin24m Rgrf@ff000000&rockchip,rk3308-grfsysconsimple-mfd Nreboot-modesyscon-reboot-mode!RB1RB=RBIRBWRB syscon@ff008000.rockchip,rk3308-usb2phy-grfsysconsimple-mfd@+usb2phy@100rockchip,rk3308-usb2phyeu Hphyclk usb480m_phy  disabled otg-port$CDEotg-bvalidotg-idlinestate disabled :host-port J linestate disabled ;syscon@ff00b000-rockchip,rk3308-detect-grfsysconsimple-mfd+syscon@ff00c000+rockchip,rk3308-core-grfsysconsimple-mfd+i2c@ff040000(rockchip,rk3308-i2crockchip,rk3399-i2c i2cpclk  default + disabledi2c@ff050000(rockchip,rk3308-i2crockchip,rk3399-i2c i2cpclk  default +okayrtc@51 nxp,pcf8563Q i2c@ff060000(rockchip,rk3308-i2crockchip,rk3399-i2c i2cpclk  default+ disabledi2c@ff070000(rockchip,rk3308-i2crockchip,rk3399-i2c i2cpclk default+ disabledwatchdog@ff080000 rockchip,rk3308-wdtsnps,dw-wdt   disabledserial@ff0a0000&rockchip,rk3308-uartsnps,dw-apb-uart  baudclkapb_pclkdefault  disabledserial@ff0b0000&rockchip,rk3308-uartsnps,dw-apb-uart  baudclkapb_pclkdefault  disabledserial@ff0c0000&rockchip,rk3308-uartsnps,dw-apb-uart  baudclkapb_pclkdefaultokayserial@ff0d0000&rockchip,rk3308-uartsnps,dw-apb-uart  baudclkapb_pclkdefault disabledserial@ff0e0000&rockchip,rk3308-uartsnps,dw-apb-uart baudclkapb_pclkdefault  disabledspi@ff120000(rockchip,rk3308-spirockchip,rk3066-spi +spiclkapb_pclktxrxdefault disabledspi@ff130000(rockchip,rk3308-spirockchip,rk3066-spi +spiclkapb_pclktxrxdefault !"# disabledspi@ff140000(rockchip,rk3308-spirockchip,rk3066-spi +spiclkapb_pclk$$txrxdefault%&'( disabledpwm@ff160000(rockchip,rk3308-pwmrockchip,rk3328-pwmy pwmpclkdefault) disabledpwm@ff160010(rockchip,rk3308-pwmrockchip,rk3328-pwmy pwmpclkdefault* disabledpwm@ff160020(rockchip,rk3308-pwmrockchip,rk3328-pwm y pwmpclkdefault+ disabledpwm@ff160030(rockchip,rk3308-pwmrockchip,rk3328-pwm0y pwmpclkdefault, disabledpwm@ff170000(rockchip,rk3308-pwmrockchip,rk3328-pwmx pwmpclkdefault- disabledpwm@ff170010(rockchip,rk3308-pwmrockchip,rk3328-pwmx pwmpclkactive.okay `pwm@ff170020(rockchip,rk3308-pwmrockchip,rk3328-pwm x pwmpclkdefault/ disabledpwm@ff170030(rockchip,rk3308-pwmrockchip,rk3328-pwm0x pwmpclkdefault0 disabledpwm@ff180000(rockchip,rk3308-pwmrockchip,rk3328-pwm pwmpclkdefault1okay epwm@ff180010(rockchip,rk3308-pwmrockchip,rk3328-pwm pwmpclkdefault2 disabledpwm@ff180020(rockchip,rk3308-pwmrockchip,rk3328-pwm  pwmpclkdefault3 disabledpwm@ff180030(rockchip,rk3308-pwmrockchip,rk3328-pwm0 pwmpclkdefault4 disabledrktimer@ff1a0000rockchip,rk3288-timer   pclktimersaradc@ff1e0000.rockchip,rk3308-saradcrockchip,rk3399-saradc %%saradcapb_pclkF saradc-apb disableddma-controller@ff2c0000arm,pl330arm,primecell,@( apb_pclk? dma-controller@ff2d0000arm,pl330arm,primecell-@( apb_pclk? $i2s@ff350000(rockchip,rk3308-i2srockchip,rk3066-i2s5 4\i2s_clki2s_hclk$$ txrxreset-mreset-hdefault5678 disabledi2s@ff360000(rockchip,rk3308-i2srockchip,rk3066-i2s6 5^i2s_clki2s_hclk$ rxreset-mreset-h disabledspdif-tx@ff3a0000,rockchip,rk3308-spdifrockchip,rk3066-spdif: 7b mclkhclk$ txdefault9 disabledusb@ff4000002rockchip,rk3308-usbrockchip,rk3066-usbsnps,dwc2@ BotgJotgRds@ : usb2-phy disabledusb@ff440000 generic-ehciD G ;usb disabledusb@ff450000 generic-ohciE H ;usb disabledmmc@ff4800000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcH@ L 012biuciuciu-driveciu-sampleрdefault<=>?okay,@Ammc@ff4900000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcI@ M :;<biuciuciu-driveciu-sampleрokay*9mmc@ff4a00000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcJ@ N 567biuciuciu-driveciu-sampleрdefault BCD disablednand-controller@ff4b0000(rockchip,rk3308-nfcrockchip,rv1108-nfcK@ Q-ahbnfce-GрEFGHIJKdefault disabledethernet@ff4e0000rockchip,rk3308-gmacN @macirq@@BBA@C[stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speed\rmiidefaultLM} stmmacetheN disabledspi@ff4c0000 rockchip,sfcL@ R=clk_sfchclk_sfc OPQdefault disabledclock-controller@ff500000rockchip,rk3308-cruPRxin24meN reG interrupt-controller@ff580000 arm,gic-400@XX X@ X`    sram@fff80000 mmio-sram+ddr-sram@0vad-sram@8000pinctrlrockchip,rk3308-pinctrleN+defaultSgpio@ff220000rockchip,gpio-bank" ( ^gpio@ff230000rockchip,gpio-bank# )gpio@ff240000rockchip,gpio-bank$ *gpio@ff250000rockchip,gpio-bank% +gpio@ff260000rockchip,gpio-bank& , cpcfg-pull-up ]pcfg-pull-down Zpcfg-pull-none Vpcfg-pull-none-2mapcfg-pull-up-2mapcfg-pull-up-4ma \pcfg-pull-none-4ma [pcfg-pull-down-4mapcfg-pull-none-8ma Tpcfg-pull-up-8ma Upcfg-pull-none-12ma  Xpcfg-pull-up-12ma  Wpcfg-pull-none-smt Ypcfg-output-highpcfg-output-low!pcfg-input-high,pcfg-input,emmcemmc-clk9 Temmc-cmd9Uemmc-pwren9 Vemmc-rstn9 Vemmc-bus19Uemmc-bus4@9UUUUemmc-bus89UUUUUUUUflashflash-csn09 V Hflash-rdy9 V Jflash-ale9 V Eflash-cle9 V Gflash-wrn9V Kflash-rdn9 V Iflash-bus89WWWWWWWW Fsfcsfc-bus4@9VVVV Qsfc-bus2 9VVsfc-cs09V Psfc-clk9V Ogmacrmii-pins9XXXVVVVV V Lmac-refclk-12ma9 X Mmac-refclk9 Vgmac-m1rmiim1-pins9XXXVVVVV Vmacm1-refclk-12ma9 Xmacm1-refclk9 Vi2c0i2c0-xfer 9YY i2c1i2c1-xfer 9 Y Y i2c2i2c2-xfer 9YY i2c3-m0i2c3m0-xfer 9YY i2c3-m1i2c3m1-xfer 9 Y Yi2c3-m2i2c3m2-xfer 9YYi2s_2ch_0i2s-2ch-0-mclk9 Vi2s-2ch-0-sclk9 V 5i2s-2ch-0-lrck9V 6i2s-2ch-0-sdo9V 8i2s-2ch-0-sdi9V 7i2s_8ch_0i2s-8ch-0-mclk9Vi2s-8ch-0-sclktx9Vi2s-8ch-0-sclkrx9Vi2s-8ch-0-lrcktx9Vi2s-8ch-0-lrckrx9Vi2s-8ch-0-sdo09 Vi2s-8ch-0-sdo19 Vi2s-8ch-0-sdo29 Vi2s-8ch-0-sdo39 Vi2s-8ch-0-sdi09 Vi2s-8ch-0-sdi19Vi2s-8ch-0-sdi29Vi2s-8ch-0-sdi39Vi2s_8ch_1_m0i2s-8ch-1-m0-mclk9Vi2s-8ch-1-m0-sclktx9Vi2s-8ch-1-m0-sclkrx9Vi2s-8ch-1-m0-lrcktx9Vi2s-8ch-1-m0-lrckrx9Vi2s-8ch-1-m0-sdo09Vi2s-8ch-1-m0-sdo1-sdi39Vi2s-8ch-1-m0-sdo2-sdi29 Vi2s-8ch-1-m0-sdo3_sdi19 Vi2s-8ch-1-m0-sdi09 Vi2s_8ch_1_m1i2s-8ch-1-m1-mclk9 Vi2s-8ch-1-m1-sclktx9 Vi2s-8ch-1-m1-sclkrx9Vi2s-8ch-1-m1-lrcktx9Vi2s-8ch-1-m1-lrckrx9Vi2s-8ch-1-m1-sdo09Vi2s-8ch-1-m1-sdo1-sdi39Vi2s-8ch-1-m1-sdo2-sdi29Vi2s-8ch-1-m1-sdo3_sdi19Vi2s-8ch-1-m1-sdi09Vpdm_m0pdm-m0-clk9Vpdm-m0-sdi09 Vpdm-m0-sdi19 Vpdm-m0-sdi29 Vpdm-m0-sdi39Vpdm_m1pdm-m1-clk9Vpdm-m1-sdi09Vpdm-m1-sdi19Vpdm-m1-sdi29Vpdm-m1-sdi39Vpdm_m2pdm-m2-clkm9Vpdm-m2-clk9Vpdm-m2-sdi09 Vpdm-m2-sdi19Vpdm-m2-sdi29Vpdm-m2-sdi39Vpwm0pwm0-pin9 Vpwm0-pin-pull-down9 Z 1pwm1pwm1-pin9V 2pwm1-pin-pull-down9Zpwm2pwm2-pin9V 3pwm2-pin-pull-down9Zpwm3pwm3-pin9V 4pwm3-pin-pull-down9Zpwm4pwm4-pin9V -pwm4-pin-pull-down9Zpwm5pwm5-pin9Vpwm5-pin-pull-down9Z .pwm6pwm6-pin9V /pwm6-pin-pull-down9Zpwm7pwm7-pin9V 0pwm7-pin-pull-down9Zpwm8pwm8-pin9 V )pwm8-pin-pull-down9 Zpwm9pwm9-pin9 V *pwm9-pin-pull-down9 Zpwm10pwm10-pin9 V +pwm10-pin-pull-down9 Zpwm11pwm11-pin9V ,pwm11-pin-pull-down9Zrtcrtc-32k9V Ssdmmcsdmmc-clk9[ <sdmmc-cmd9\ =sdmmc-det9\ >sdmmc-pwren9[sdmmc-bus19\sdmmc-bus4@9\\\\ ?sdiosdio-clk9T Dsdio-cmd9U Csdio-pwren9Tsdio-wrpt9Tsdio-intn9Tsdio-bus19Usdio-bus4@9UUUU Bspdif_inspdif-in9Vspdif_outspdif-out9V 9spi0spi0-clk9\ spi0-csn09\ spi0-miso9\ spi0-mosi9\ spi1spi1-clk9 \ spi1-csn09 \ !spi1-miso9 \ "spi1-mosi9 \ #spi1-m1spi1m1-miso9\spi1m1-mosi9\spi1m1-clk9\spi1m1-csn09 \spi2spi2-clk9\ %spi2-csn09\ &spi2-miso9\ 'spi2-mosi9\ (tsadctsadc-otp-pin9 Vtsadc-otp-out9 Vuart0uart0-xfer 9]] uart0-cts9V uart0-rts9V uart0-rts-pin9Vuart1uart1-xfer 9]] uart1-cts9V uart1-rts9V uart2-m0uart2m0-xfer 9]] uart2-m1uart2m1-xfer 9]]uart3uart3-xfer 9 ] ] uart3-m1uart3m1-xfer 9]]uart4uart4-xfer 9 ]] uart4-cts9V uart4-rts9V uart4-rts-pin9Vir-receiverir-recv-pin9V _buttonspwr-key9]chosenGserial2:1500000n8ir-receivergpio-ir-receiver S^default_ir_tx pwm-ir-txY`aleds gpio-ledsled-0^firefly:red:powerdir-power-clickzon S^led-1^firefly:blue:userdir-user-clickzoff S^ typec-vcc5vregulator-fixed typec_vcc5vLK@LK@ avcc5v0-sysregulator-fixed vcc5v0_sysLK@LK@a bvcc-ioregulator-fixedvcc_io2Z2Zb dvcc-sdmmcregulator-gpio vcc_sdmmcw@2Z S^w@2Zb Avcc-sdregulator-fixed cvcc_sd2Z2Zd @vdd-corepwm-regulatorYe vdd_core xr`|4b vdd-logregulator-fixedvdd_logb compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4spi0spi1spi2mmc0mmc1device_typeregenable-methodclocks#cooling-cellsdynamic-power-coefficientoperating-points-v2cpu-idle-statesnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsoffsetmode-bootloadermode-loadermode-normalmode-recoverymode-fastbootassigned-clocksassigned-clock-parentsclock-namesstatusinterrupt-names#phy-cellspinctrl-namespinctrl-0reg-shiftreg-io-widthdmasdma-names#pwm-cells#io-channel-cellsresetsreset-namesarm,pl330-periph-burst#dma-cellsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesbus-widthfifo-depthmax-frequencycap-mmc-highspeedcap-sd-highspeedcard-detect-delaysd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplymmc-hs200-1_8vnon-removableassigned-clock-ratesphy-moderockchip,grf#reset-cells#interrupt-cellsinterrupt-controllerrangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathgpiospwmslabellinux,default-triggerdefault-stateregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onvin-supplygpioregulator-init-microvoltregulator-settling-time-up-uspwm-supply