~O8w|(wDradxa,rockpisrockchip,rk3308 +7Radxa ROCK Pi Saliases=/i2c@ff040000B/i2c@ff050000G/i2c@ff060000L/i2c@ff070000Q/serial@ff0a0000Y/serial@ff0b0000a/serial@ff0c0000i/serial@ff0d0000q/serial@ff0e0000y/spi@ff120000~/spi@ff130000/spi@ff140000/ethernet@ff4e0000/mmc@ff490000/mmc@ff480000cpus+cpu@0cpuarm,cortex-a35psciZ*cpu@1cpuarm,cortex-a35psci*cpu@2cpuarm,cortex-a35psci* cpu@3cpuarm,cortex-a35psci* idle-states2pscicpu-sleeparm,idle-state?Pgxx*l2-cachecache*opp-table-0operating-points-v2*opp-408000000Q ~~r`@opp-600000000#F ~~r`@opp-8160000000, r`@opp-1008000000< **r`@arm-pmuarm,cortex-a35-pmu0STUV external-mac-clock fixed-clock mac_clkinpsci arm,psci-1.0smctimerarm,armv8-timer0   xin24m fixed-clockn6xin24m*Vgrf@ff000000&rockchip,rk3308-grfsysconsimple-mfd*Qreboot-modesyscon-reboot-mode$+RB;RBGRBSRBaRB syscon@ff008000.rockchip,rk3308-usb2phy-grfsysconsimple-mfd@+usb2phy@100rockchip,rk3308-usb2phyo Hphyclk usb480m_phyokay* otg-port$CDEotg-bvalidotg-idlinestateokay *=host-port J linestateokay *>syscon@ff00b000-rockchip,rk3308-detect-grfsysconsimple-mfd+syscon@ff00c000+rockchip,rk3308-core-grfsysconsimple-mfd+i2c@ff040000(rockchip,rk3308-i2crockchip,rk3399-i2c i2cpclk  default + disabledi2c@ff050000(rockchip,rk3308-i2crockchip,rk3399-i2c i2cpclk  default+okayi2c@ff060000(rockchip,rk3308-i2crockchip,rk3399-i2c i2cpclk  default+ disabledi2c@ff070000(rockchip,rk3308-i2crockchip,rk3399-i2c i2cpclk default+ disabledwatchdog@ff080000 rockchip,rk3308-wdtsnps,dw-wdt  okayserial@ff0a0000&rockchip,rk3308-uartsnps,dw-apb-uart  baudclkapb_pclkdefault okayserial@ff0b0000&rockchip,rk3308-uartsnps,dw-apb-uart  baudclkapb_pclkdefault  disabledserial@ff0c0000&rockchip,rk3308-uartsnps,dw-apb-uart  baudclkapb_pclkdefault disabledserial@ff0d0000&rockchip,rk3308-uartsnps,dw-apb-uart  baudclkapb_pclkdefault disabledserial@ff0e0000&rockchip,rk3308-uartsnps,dw-apb-uart baudclkapb_pclkdefault okaybluetoothrealtek,rtl8723bs-bt    spi@ff120000(rockchip,rk3308-spirockchip,rk3066-spi +spiclkapb_pclk %txrxdefault ! disabledspi@ff130000(rockchip,rk3308-spirockchip,rk3066-spi +spiclkapb_pclk %txrxdefault"#$% disabledspi@ff140000(rockchip,rk3308-spirockchip,rk3066-spi +spiclkapb_pclk &&%txrxdefault'()* disabledpwm@ff160000(rockchip,rk3308-pwmrockchip,rk3328-pwmy pwmpclkdefault+/ disabledpwm@ff160010(rockchip,rk3308-pwmrockchip,rk3328-pwmy pwmpclkdefault,/ disabledpwm@ff160020(rockchip,rk3308-pwmrockchip,rk3328-pwm y pwmpclkdefault-/ disabledpwm@ff160030(rockchip,rk3308-pwmrockchip,rk3328-pwm0y pwmpclkdefault./ disabledpwm@ff170000(rockchip,rk3308-pwmrockchip,rk3328-pwmx pwmpclkdefault// disabledpwm@ff170010(rockchip,rk3308-pwmrockchip,rk3328-pwmx pwmpclkdefault0/ disabledpwm@ff170020(rockchip,rk3308-pwmrockchip,rk3328-pwm x pwmpclkdefault1/ disabledpwm@ff170030(rockchip,rk3308-pwmrockchip,rk3328-pwm0x pwmpclkdefault2/ disabledpwm@ff180000(rockchip,rk3308-pwmrockchip,rk3328-pwm pwmpclkdefault3/okay*gpwm@ff180010(rockchip,rk3308-pwmrockchip,rk3328-pwm pwmpclkdefault4/ disabledpwm@ff180020(rockchip,rk3308-pwmrockchip,rk3328-pwm  pwmpclkdefault5/ disabledpwm@ff180030(rockchip,rk3308-pwmrockchip,rk3328-pwm0 pwmpclkdefault6/ disabledrktimer@ff1a0000rockchip,rk3288-timer   pclktimersaradc@ff1e0000.rockchip,rk3308-saradcrockchip,rk3399-saradc %%saradcapb_pclk:LF Ssaradc-apbokay_7dma-controller@ff2c0000arm,pl330arm,primecell,@k apb_pclk*dma-controller@ff2d0000arm,pl330arm,primecell-@k apb_pclk*&i2s@ff350000(rockchip,rk3308-i2srockchip,rk3066-i2s5 4\i2s_clki2s_hclk && %txrxLSreset-mreset-hdefault89:; disabledi2s@ff360000(rockchip,rk3308-i2srockchip,rk3066-i2s6 5^i2s_clki2s_hclk & %rxLSreset-mreset-h disabledspdif-tx@ff3a0000,rockchip,rk3308-spdifrockchip,rk3066-spdif: 7b mclkhclk & %txdefault< disabledusb@ff4000002rockchip,rk3308-usbrockchip,rk3066-usbsnps,dwc2@ Botg peripheral@ = usb2-phyokayusb@ff440000 generic-ehciD G >usbokayusb@ff450000 generic-ohciE H >usbokaymmc@ff4800000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcH@ L 012biuciuciu-driveciu-sampleрdefault?@ABokaymmc@ff4900000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcI@ M :;<biuciuciu-driveciu-sampleрokay)7Cmmc@ff4a00000rockchip,rk3308-dw-mshcrockchip,rk3288-dw-mshcJ@ N 567biuciuciu-driveciu-sampleB@default DEFokay+CPfG)qnand-controller@ff4b0000(rockchip,rk3308-nfcrockchip,rv1108-nfcK@ Q-ahbnfco-рHIJKLMNdefault disabledethernet@ff4e0000rockchip,rk3308-gmacN @macirq@@BBA@C[stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speedrmiidefaultOPL} SstmmacethQokayoutputC R PPspi@ff4c0000 rockchip,sfcL@ R=clk_sfchclk_sfc STUdefault disabledclock-controller@ff500000rockchip,rk3308-cruPVxin24mQo*interrupt-controller@ff580000 arm,gic-400@XX X@ X`   *sram@fff80000 mmio-sram%+ddr-sram@0vad-sram@8000pinctrlrockchip,rk3308-pinctrlQ+%defaultWgpio@ff220000rockchip,gpio-bank" (,<*Rgpio@ff230000rockchip,gpio-bank# ),<gpio@ff240000rockchip,gpio-bank$ *,<gpio@ff250000rockchip,gpio-bank% +,<gpio@ff260000rockchip,gpio-bank& ,,<*pcfg-pull-upH*apcfg-pull-downU*^pcfg-pull-noned*Zpcfg-pull-none-2madqpcfg-pull-up-2maHqpcfg-pull-up-4maHq*`pcfg-pull-none-4madq*_pcfg-pull-down-4maUqpcfg-pull-none-8madq*Xpcfg-pull-up-8maHq*Ypcfg-pull-none-12madq *\pcfg-pull-up-12maHq *[pcfg-pull-none-smtd*]pcfg-output-highpcfg-output-lowpcfg-input-highHpcfg-inputemmcemmc-clk Xemmc-cmdYemmc-pwren Zemmc-rstn Zemmc-bus1Yemmc-bus4@YYYYemmc-bus8YYYYYYYYflashflash-csn0 Z*Kflash-rdy Z*Mflash-ale Z*Hflash-cle Z*Jflash-wrnZ*Nflash-rdn Z*Lflash-bus8[[[[[[[[*Isfcsfc-bus4@ZZZZ*Usfc-bus2 ZZsfc-cs0Z*Tsfc-clkZ*Sgmacrmii-pins\\\ZZZZZ Z*Omac-refclk-12ma \*Pmac-refclk Zgmac-m1rmiim1-pins\\\ZZZZZ Zmacm1-refclk-12ma \macm1-refclk Zi2c0i2c0-xfer ]]* i2c1i2c1-xfer  ] ]*i2c2i2c2-xfer ]]*i2c3-m0i2c3m0-xfer ]]*i2c3-m1i2c3m1-xfer  ] ]i2c3-m2i2c3m2-xfer ]]i2s_2ch_0i2s-2ch-0-mclk Zi2s-2ch-0-sclk Z*8i2s-2ch-0-lrckZ*9i2s-2ch-0-sdoZ*;i2s-2ch-0-sdiZ*:i2s_8ch_0i2s-8ch-0-mclkZi2s-8ch-0-sclktxZi2s-8ch-0-sclkrxZi2s-8ch-0-lrcktxZi2s-8ch-0-lrckrxZi2s-8ch-0-sdo0 Zi2s-8ch-0-sdo1 Zi2s-8ch-0-sdo2 Zi2s-8ch-0-sdo3 Zi2s-8ch-0-sdi0 Zi2s-8ch-0-sdi1Zi2s-8ch-0-sdi2Zi2s-8ch-0-sdi3Zi2s_8ch_1_m0i2s-8ch-1-m0-mclkZi2s-8ch-1-m0-sclktxZi2s-8ch-1-m0-sclkrxZi2s-8ch-1-m0-lrcktxZi2s-8ch-1-m0-lrckrxZi2s-8ch-1-m0-sdo0Zi2s-8ch-1-m0-sdo1-sdi3Zi2s-8ch-1-m0-sdo2-sdi2 Zi2s-8ch-1-m0-sdo3_sdi1 Zi2s-8ch-1-m0-sdi0 Zi2s_8ch_1_m1i2s-8ch-1-m1-mclk Zi2s-8ch-1-m1-sclktx Zi2s-8ch-1-m1-sclkrxZi2s-8ch-1-m1-lrcktxZi2s-8ch-1-m1-lrckrxZi2s-8ch-1-m1-sdo0Zi2s-8ch-1-m1-sdo1-sdi3Zi2s-8ch-1-m1-sdo2-sdi2Zi2s-8ch-1-m1-sdo3_sdi1Zi2s-8ch-1-m1-sdi0Zpdm_m0pdm-m0-clkZpdm-m0-sdi0 Zpdm-m0-sdi1 Zpdm-m0-sdi2 Zpdm-m0-sdi3Zpdm_m1pdm-m1-clkZpdm-m1-sdi0Zpdm-m1-sdi1Zpdm-m1-sdi2Zpdm-m1-sdi3Zpdm_m2pdm-m2-clkmZpdm-m2-clkZpdm-m2-sdi0 Zpdm-m2-sdi1Zpdm-m2-sdi2Zpdm-m2-sdi3Zpwm0pwm0-pin Zpwm0-pin-pull-down ^*3pwm1pwm1-pinZ*4pwm1-pin-pull-down^pwm2pwm2-pinZ*5pwm2-pin-pull-down^pwm3pwm3-pinZ*6pwm3-pin-pull-down^pwm4pwm4-pinZ*/pwm4-pin-pull-down^pwm5pwm5-pinZ*0pwm5-pin-pull-down^pwm6pwm6-pinZ*1pwm6-pin-pull-down^pwm7pwm7-pinZ*2pwm7-pin-pull-down^pwm8pwm8-pin Z*+pwm8-pin-pull-down ^pwm9pwm9-pin Z*,pwm9-pin-pull-down ^pwm10pwm10-pin Z*-pwm10-pin-pull-down ^pwm11pwm11-pinZ*.pwm11-pin-pull-down^rtcrtc-32kZ*Wsdmmcsdmmc-clk_*?sdmmc-cmd`*@sdmmc-det`*Asdmmc-pwren_sdmmc-bus1`sdmmc-bus4@````*Bsdiosdio-clkX*Fsdio-cmdY*Esdio-pwrenXsdio-wrptXsdio-intnXsdio-bus1Ysdio-bus4@YYYY*Dspdif_inspdif-inZspdif_outspdif-outZ*<spi0spi0-clk`*spi0-csn0`*spi0-miso`* spi0-mosi`*!spi1spi1-clk `*"spi1-csn0 `*#spi1-miso `*$spi1-mosi `*%spi1-m1spi1m1-miso`spi1m1-mosi`spi1m1-clk`spi1m1-csn0 `spi2spi2-clk`*'spi2-csn0`*(spi2-miso`*)spi2-mosi`**tsadctsadc-otp-pin Ztsadc-otp-out Zuart0uart0-xfer aa*uart0-ctsZ*uart0-rtsZ*uart0-rts-pinZuart1uart1-xfer aa*uart1-ctsZ*uart1-rtsZ*uart2-m0uart2m0-xfer aa*uart2-m1uart2m1-xfer aauart3uart3-xfer  a a*uart3-m1uart3m1-xfer aauart4uart4-xfer  aa*uart4-ctsZ*uart4-rtsZ*uart4-rts-pinZledsgreen-led-gpioZ*bheartbeat-led-gpioZ*cusbotg-vbus-drvZ*fsdio-pwrseqwifi-enable-hZ*dwifi-host-wake^chosenserial0:1500000n8leds gpio-ledsdefaultbcgreen-ledon  Rrockpis:green:power default-onblue-ledon  Rrockpis:blue:user heartbeatsdio-pwrseqmmc-pwrseq-simpleddefault R*Gvcc-1v8regulator-fixed vcc_1v8,>w@Vw@nC*7vcc-ioregulator-fixed vcc_io,>2ZV2Zne*Cvcc-ddrregulator-fixed vcc_ddr,>`V`nevcc5v0-otgregulator-fixedy Rdefaultf  vcc5v0_otgne* vcc5v0-sysregulator-fixed  vcc5v0_sys,>LK@VLK@*evdd-corepwm-regulatorge  vdd_core> xVr`|,*vdd-logregulator-fixed vdd_log,>Vne compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4spi0spi1spi2ethernet0mmc0mmc1device_typeregenable-methodclocks#cooling-cellsdynamic-power-coefficientoperating-points-v2cpu-idle-statesnext-level-cachecpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityclock-frequencyclock-output-names#clock-cellsoffsetmode-bootloadermode-loadermode-normalmode-recoverymode-fastbootassigned-clocksassigned-clock-parentsclock-namesstatusinterrupt-names#phy-cellsphy-supplypinctrl-namespinctrl-0reg-shiftreg-io-widthdevice-wake-gpioshost-wake-gpiosdmasdma-names#pwm-cells#io-channel-cellsresetsreset-namesvref-supplyarm,pl330-periph-burst#dma-cellsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesbus-widthfifo-depthmax-frequencycap-sd-highspeedcap-mmc-highspeedmmc-hs200-1_8vnon-removablevmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqsd-uhs-sdr104assigned-clock-ratesphy-moderockchip,grfclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-us#reset-cells#interrupt-cellsinterrupt-controllerrangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathdefault-statelabellinux,default-triggerreset-gpiosregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltvin-supplyenable-active-highpwmspwm-supplyregulator-init-microvoltregulator-settling-time-up-us