8( pine64,rock64rockchip,rk3328 +7Pine64 Rock64aliases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/ethernet@ff550000}/mmc@ff500000/mmc@ff520000cpus+cpu@0cpuarm,cortex-a53xpsci  cpu@1cpuarm,cortex-a53xpsci  cpu@2cpuarm,cortex-a53xpsci  cpu@3cpuarm,cortex-a53xpsci  idle-statespscicpu-sleeparm,idle-state*;Rxcsl2-cache0cacheopp-table-0operating-points-v2opp-408000000Q~@opp-600000000#F~@opp-8160000000,B@@opp-1008000000<@opp-1200000000G(@opp-1296000000M?d @analog-soundsimple-audio-cardi2sAnalog okaysimple-audio-card,cpusimple-audio-card,codecarm-pmuarm,cortex-a53-pmu0defg' display-subsystemrockchip,display-subsystem: hdmi-soundsimple-audio-cardi2sHDMI okaysimple-audio-card,cpusimple-audio-card,codecpsciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer0   xin24m fixed-clock@Mn6]xin24mEi2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s )7pi2s_clki2s_hclk|  txrx okayi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s *8pi2s_clki2s_hclk|txrx okayi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s +9pi2s_clki2s_hclk|txrx  disabledspdif@ff030000rockchip,rk3328-spdif .: pmclkhclk| txdefault okayhpdm@ff040000 rockchip,pdm=Rppdm_clkpdm_hclk|rxdefaultsleep  disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd9io-domains"rockchip,rk3328-io-voltage-domain okaygpiorockchip,rk3328-grf-gpio/Dpower-controller!rockchip,rk3328-power-controller;+;power-domain@6;power-domain@5 BAB;power-domain@8F;reboot-modesyscon-reboot-modeOVRBbRBpRB RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart 7&pbaudclkapb_pclk|txrxdefault  !  disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart 8'pbaudclkapb_pclk|txrxdefault "#$  disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart 9(pbaudclkapb_pclk|txrxdefault% okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c $+7 pi2cpclkdefault&  disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c %+8 pi2cpclkdefault' okaypmic@18rockchip,rk805 (@]xin32krk805-clkout2/default)*****gregulatorsDCDC_REG1 vdd_logic) 4A Y0nregulator-state-memB@DCDC_REG2vdd_arm) 4A Y0nregulator-state-mem~DCDC_REG3vcc_ddrnregulator-state-memDCDC_REG4vcc_io)2ZA2Znregulator-state-mem2ZLDO_REG1vcc_18)w@Aw@nregulator-state-memw@LDO_REG2 vcc18_emmc)w@Aw@nregulator-state-memw@LDO_REG3vdd_10)B@AB@nregulator-state-memB@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c &+9 pi2cpclkdefault+  disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c '+: pi2cpclkdefault,  disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi 1+ pspiclkapb_pclk| txrxdefault-./0 okayflash@0jedec,spi-norwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt (pwm@ff1b0000rockchip,rk3328-pwm< ppwmpclkdefault1  disabledpwm@ff1b0010rockchip,rk3328-pwm< ppwmpclkdefault2  disabledpwm@ff1b0020rockchip,rk3328-pwm < ppwmpclkdefault3  disabledpwm@ff1b0030rockchip,rk3328-pwm0 2< ppwmpclkdefault4  disableddma-controller@ff1f0000arm,pl330arm,primecell@ papb_pclkthermal-zonessoc-thermal+=5tripstrip-point0MpYpassivetrip-point1MLYpassive6soc-critMsY criticalcooling-mapsmap0d60i xtsadc@ff250000rockchip,rk3328-tsadc% :$P$ptsadcapb_pclkinitdefaultsleep787B tsadc-apb9 okay5efuse@ff260000rockchip,rk3328-efuse&P+> ppclk_efuse3 id@7cpu-leakage@17logic-leakage@19cpu-version@1aGFadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc( PL%psaradcapb_pclkV saradc-apb  disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-4500TZW]XY[\"^gpgpmmupppp0ppmmu0pp1ppmmu1 pbuscorefiommu@ff330200rockchip,iommu3 ` paclkifacen  disablediommu@ff340800rockchip,iommu4@ bF paclkifacen  disabledvideo-codec@ff350000rockchip,rk3328-vpu5  ^vdpuF paclkhclk{:;iommu@ff350800rockchip,iommu5@  F paclkifacen;:video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec6  BABpaxiahbcabaccoreAB ׄׄ{<;iommu@ff360480rockchip,iommu 6@6@ JB paclkifacen;<vop@ff370000rockchip,rk3328-vop7>  x;paclk_vopdclk_vophclk_vop axiahbdclk{= okayport+ endpoint@0>Ciommu@ff373f00rockchip,iommu7?  ; paclkifacen okay=hdmi@ff3c0000rockchip,rk3328-dw-hdmi<#GFpiahbisfrcec?hdmidefault @AB9 okayportsportendpointC>codec@ff410000rockchip,rk3328-codecA* ppclkmclk9 okay Dphy@ff430000rockchip,rk3328-hdmi-phyC SEypsysclkrefoclkrefpclk ]hdmi_phy@F cpu-version okay?clock-controller@ff440000(rockchip,rk3328-crurockchip,crusysconD9@x=&'(ABDC"\5H4$zEEE|n6n6n6n6#FLGрxhxhрxhxhsyscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfdE+usb2phy@100rockchip,rk3328-usb2phyEpphyclk ]usb480m_phy@{G okayGotg-port$;<=^otg-bvalidotg-idlinestate okayVhost-port > ^linestate okayWmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcP@   =!JNpbiuciuciu-driveciu-sampleр okay->defaultHIJKILmmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcQ@   >"KOpbiuciuciu-driveciu-sampleр  disabledmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcR@  ?#LPpbiuciuciu-driveciu-sampleр okayUddefault MNOIrethernet@ff540000rockchip,rk3328-gmacT ^macirq8dWXZYMpstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macc stmmaceth9 okaydfPPinputrgmiidefaultQ R 'P$ ethernet@ff550000rockchip,rk3328-gmacU9 ^macirq8TSSUVIpstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphyb stmmacethrmiiSoutput  disabledmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22VddefaultTUSusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2X Mpotg0host8JY@ V usb2-phy okayusb@ff5c0000 generic-ehci\  NGWusb okayusb@ff5d0000 generic-ohci]  NGWusb okayusb@ff600000rockchip,rk3328-dwc3snps,dwc3` C`apref_clksuspend_clkbus_clk0host hutmi_wideq  okayinterrupt-controller@ff811000 arm,gic-400  0@ @ `   pinctrlrockchip,rk3328-pinctrl9+ Egpio@ff210000rockchip,gpio-bank! 3/ 0 cgpio@ff220000rockchip,gpio-bank" 4/ 0 Rgpio@ff230000rockchip,gpio-bank# 5/ 0 (gpio@ff240000rockchip,gpio-bank$ 6/ 0 pcfg-pull-up LZpcfg-pull-down Ybpcfg-pull-none hXpcfg-pull-none-2ma h uapcfg-pull-up-2ma L upcfg-pull-up-4ma L u[pcfg-pull-none-4ma h u^pcfg-pull-down-4ma Y upcfg-pull-none-8ma h u\pcfg-pull-up-8ma L u]pcfg-pull-none-12ma h u _pcfg-pull-up-12ma L u `pcfg-output-high pcfg-output-low pcfg-input-high L Ypcfg-input i2c0i2c0-xfer XX&i2c1i2c1-xfer XX'i2c2i2c2-xfer  XX+i2c3i2c3-xfer XX,i2c3-pins XXhdmi_i2chdmii2c-xfer XXApdm-0pdmm0-clk Xpdmm0-fsync Xpdmm0-sdi0 Xpdmm0-sdi1 Xpdmm0-sdi2 Xpdmm0-sdi3 Xpdmm0-clk-sleep Ypdmm0-sdi0-sleep Ypdmm0-sdi1-sleep Ypdmm0-sdi2-sleep Ypdmm0-sdi3-sleep Ypdmm0-fsync-sleep Ytsadcotp-pin  X7otp-out  X8uart0uart0-xfer  XZuart0-cts  X uart0-rts  X!uart0-rts-pin  Xuart1uart1-xfer XZ"uart1-cts X#uart1-rts X$uart1-rts-pin Xuart2-0uart2m0-xfer XZuart2-1uart2m1-xfer XZ%spi0-0spi0m0-clk Zspi0m0-cs0  Zspi0m0-tx  Zspi0m0-rx  Zspi0m0-cs1  Zspi0-1spi0m1-clk Zspi0m1-cs0 Zspi0m1-tx Zspi0m1-rx Zspi0m1-cs1 Zspi0-2spi0m2-clk Z-spi0m2-cs0 Z0spi0m2-tx Z.spi0m2-rx Z/i2s1i2s1-mclk Xi2s1-sclk Xi2s1-lrckrx Xi2s1-lrcktx Xi2s1-sdi Xi2s1-sdo Xi2s1-sdio1 Xi2s1-sdio2 Xi2s1-sdio3 Xi2s1-sleep YYYYYYYYYi2s2-0i2s2m0-mclk Xi2s2m0-sclk Xi2s2m0-lrckrx Xi2s2m0-lrcktx Xi2s2m0-sdi Xi2s2m0-sdo Xi2s2m0-sleep` YYYYYYi2s2-1i2s2m1-mclk Xi2s2m1-sclk Xi2sm1-lrckrx Xi2s2m1-lrcktx Xi2s2m1-sdi Xi2s2m1-sdo Xi2s2m1-sleepP YYYYYspdif-0spdifm0-tx Xspdif-1spdifm1-tx Xspdif-2spdifm2-tx Xsdmmc0-0sdmmc0m0-pwren [sdmmc0m0-pin [sdmmc0-1sdmmc0m1-pwren [sdmmc0m1-pin [dsdmmc0sdmmc0-clk \Hsdmmc0-cmd ]Isdmmc0-dectn [Jsdmmc0-wrprt [sdmmc0-bus1 ]sdmmc0-bus4@ ]]]]Ksdmmc0-pins [[[[[[[[sdmmc0extsdmmc0ext-clk ^sdmmc0ext-cmd [sdmmc0ext-wrprt [sdmmc0ext-dectn [sdmmc0ext-bus1 [sdmmc0ext-bus4@ [[[[sdmmc0ext-pins [[[[[[[[sdmmc1sdmmc1-clk  \sdmmc1-cmd  ]sdmmc1-pwren ]sdmmc1-wrprt ]sdmmc1-dectn ]sdmmc1-bus1 ]sdmmc1-bus4@ ]]]]sdmmc1-pins  [ [[[[[[[[emmcemmc-clk _Memmc-cmd `Nemmc-pwren Xemmc-rstnout Xemmc-bus1 `emmc-bus4@ ````emmc-bus8 ````````Opwm0pwm0-pin X1pwm1pwm1-pin X2pwm2pwm2-pin X3pwmirpwmir-pin X4gmac-1rgmiim1-pins`  \ ^^\^^^ ^ ^\ \^^\\\ \^\\\\Qrmiim1-pins a_aaaa a a_ _ X XXXXXgmac2phyfephyled-speed10 Xfephyled-duplex Xfephyled-rxm1 XTfephyled-txm1 Xfephyled-linkm1 XUtsadc_pintsadc-int  Xtsadc-pin  Xhdmi_pinhdmi-cec X@hdmi-hpd bBcif-0dvp-d2d9-m0 XXXXX X X XXXXXcif-1dvp-d2d9-m1 XXXXXXXXXXXXirir-int Xfpmicpmic-int-l Z)usb2usb20-host-drv Xechosen serial2:1500000n8external-gmac-clock fixed-clockMsY@ ]gmac_clkin@Psdmmc-regulatorregulator-fixed cdefaultdvcc_sd)2ZA2Z Lvcc-host-5v-regulatorregulator-fixed cdefaulte vcc_host_5vn *vcc-host1-5v-regulatorregulator-fixed cdefaulte vcc_host1_5vn *vcc-sysregulator-fixedvcc_sysn)LK@ALK@*ir-receivergpio-ir-receiver (fdefaultleds gpio-ledsled-0 g mmc0led-1 g heartbeatspdif-soundsimple-audio-cardSPDIFsimple-audio-card,cpuhsimple-audio-card,codecispdif-ditlinux,spdif-diti compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1mmc0mmc1device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1vccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplypmuio-supplygpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvoltspi-max-frequency#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarityrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesmute-gpiosnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthbus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvmmc-supplymmc-hs200-1_8vnon-removablevqmmc-supplysnps,txpblclock_in_outphy-supplyphy-modesnps,force_thresh_dma_modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayphy-handlephy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathvin-supplylinux,default-trigger