Ð þí `8 ´(¬ | !,ARM Corstone1000 FPGA MPS3 board2arm,corstone1000-mps3aliases=/soc/serial@1a510000E/soc/serial@1a520000chosenMserial0:115200n8cpus cpu@0Ycpu2arm,cortex-a35eimemory@88200000Ymemoryeˆ wàinterrupt-controller@1c000000 2arm,gic-400z‹ eð ðð    «l2-cache02cache³¿Ê@Ú«refclk100mhz 2fixed-clockåòõá apb_pclk«refclk24mhzx2 2fixed-clockåòÜlsmclktimer2arm,armv8-timer0    uartclk 2fixed-clockåòúð€uartclk«psci2arm,psci-1.0arm,psci-0.2smcsoc 2simple-bus timer@1a2200002arm,armv7-timer-meme" òúð€frame@1a230000#  e#serial@1a5100002arm,pl011arm,primecelleQ  07uartclkapb_pclkserial@1a5200002arm,pl011arm,primecelleR  07uartclkapb_pclkmailbox@1b8200002arm,mhuv2-txarm,primecelle‚0 7apb_pclk  -COcokay jdisabledmailbox@1b8300002arm,mhuv2-rxarm,primecelleƒ0 7apb_pclk  .COcokay jdisabledethernet@40100002smsc,lan9220smsc,lan9115e@qmii  tz‡usb@402000002nxp,usb-isp1763e@   rš¤host interrupt-parent#address-cells#size-cellsmodelcompatibleserial0serial1stdout-pathdevice_typeregnext-level-cache#interrupt-cellsinterrupt-controllerinterruptsphandlecache-levelcache-sizecache-line-sizecache-sets#clock-cellsclock-frequencyclock-output-namesmethodrangesframe-numberclocksclock-names#mbox-cellsarm,mhuv2-protocolssecure-statusphy-modereg-io-widthsmsc,irq-push-pullbus-widthdr_mode