O8(`$mediatek,mt6795-evbmediatek,mt6795 +!7MediaTek MT6795 Evaluation Boardpsci arm,psci-0.2=smccpus+cpu@0Dcpuarm,cortex-a53Ppsci^bscpu@1Dcpuarm,cortex-a53Ppsci^bscpu@2Dcpuarm,cortex-a53Ppsci^bscpu@3Dcpuarm,cortex-a53Ppsci^bs cpu@100Dcpuarm,cortex-a53Ppsci^bs cpu@101Dcpuarm,cortex-a53Ppsci^bs cpu@102Dcpuarm,cortex-a53Ppsci^bs cpu@103Dcpuarm,cortex-a53Ppsci^bs cpu-mapcluster0core0core1core2core3 cluster1core0 core1 core2 core3 l2-cache0cachel2-cache1cacheoscillator-26m fixed-clockclk26moscillator-32k fixed-clock}clk32kdummy13m fixed-clock]@pmuarm,cortex-a53-pmu0    timerarm,armv8-timer 0   soc+ simple-buspinctrl@10005000mediatek,mt6795-pinctrl ^P baseeint #8watchdog@10007000mediatek,mt6795-wdt^p IVtimer@10008000,mediatek,mt6795-timermediatek,mt6577-timer^ bintpol-controller@10200620.mediatek,mt6795-sysirqmediatek,mt6577-sysirq#8 ^  timer@10200670mediatek,mt6795-systimer^ p @biclk13minterrupt-controller@10221000 arm,gic-4008 #@^"" "@ "`   cci@10390000 arm,cci-400+^99slave-if@1000arm,cci-400-ctrl-if uace-lite^slave-if@4000arm,cci-400-ctrl-ifuace^@slave-if@5000arm,cci-400-ctrl-ifuace^Ppmu@9000arm,cci-400-pmu,r1^P<:;<=>serial@11002000*mediatek,mt6795-uartmediatek,mt6577-uart^  [bokayserial@11003000*mediatek,mt6795-uartmediatek,mt6577-uart^0 \b disabledserial@11004000*mediatek,mt6795-uartmediatek,mt6577-uart^@ ]b disabledserial@11005000*mediatek,mt6795-uartmediatek,mt6577-uart^P ^b disabledaliases/soc/serial@11002000/soc/serial@11003000/soc/serial@11004000/soc/serial@11005000memory@40000000Dmemory^@chosenserial0:921600n8 compatibleinterrupt-parent#address-cells#size-cellsmodelmethoddevice_typeenable-methodregcci-control-portnext-level-cachephandlecpucache-level#clock-cellsclock-frequencyclock-output-namesinterruptsinterrupt-affinityrangesreg-namesgpio-controller#gpio-cellsgpio-rangesinterrupt-controller#interrupt-cells#reset-cellstimeout-secclocksclock-namesinterface-typestatusserial0serial1serial2serial3stdout-path