B28?(( >$mediatek,mt8186-evbmediatek,mt8186 +!7MediaTek MT8186 evaluation boardcpus+cpu-mapcluster0core0=core1=core2=core3=core4=core5=core6=core7= cpu@0Acpuarm,cortex-a55MQpsci_w5o~  cpu@100Acpuarm,cortex-a55MQpsci_w5o~  cpu@200Acpuarm,cortex-a55MQpsci_w5o~  cpu@300Acpuarm,cortex-a55MQpsci_w5o~  cpu@400Acpuarm,cortex-a55MQpsci_w5o~  cpu@500Acpuarm,cortex-a55MQpsci_w5o~  cpu@600Acpuarm,cortex-a76MQpsci_z0o cpu@700Acpuarm,cortex-a76MQpsci_z0o  idle-statespscicpu-off-larm,idle-state2d@ cpu-off-barm,idle-state2dx cluster-off-larm,idle-stated4 cluster-off-barm,idle-statedll2-cache0cache l2-cache1cachel3-cachecachefixed-factor-clock-13mfixed-factor-clock!.5?Jclk13moscillator-26m fixed-clock!_Jclk26moscillator-32k fixed-clock!_Jclk32kpmu-a55arm,cortex-a55-pmu ]pmu-a76arm,cortex-a76-pmu ]psci arm,psci-1.0Xsmctimerarm,armv8-timer @]   soc+ simple-bushinterrupt-controller@c000000 arm,gic-v3o  M   ] ppi-partitionsinterrupt-partition-0interrupt-partition-1 syscon@c53a000mediatek,mt8186-mcusyssysconM S!syscon@10000000 mediatek,mt8186-topckgensysconM!syscon@10001000#mediatek,mt8186-infracfg_aosysconM!syscon@10003000mediatek,mt8186-pericfgsysconM0pinctrl@10005000mediatek,mt8186-pinctrlMP "$&*,Biocfg0iocfg_ltiocfg_lmiocfg_lbiocfg_bliocfg_rbiocfg_rteint]oi2c0-default-pinspins-bus i2c1-default-pinspins-bus i2c2-default-pinspins-bus i2c3-default-pinspins-bus i2c4-default-pinspins-bus i2c5-default-pinspins-bus i2c6-default-pinspins-bus- i2c7-default-pins pins-bus i2c8-default-pins!pins-bus i2c9-default-pins"pins-bus- watchdog@10007000mediatek,mt8186-wdt:Mpsyscon@1000c000"mediatek,mt8186-apmixedsyssysconM!#pwrap@1000d000mediatek,mt8186-pwrapsysconMpwrap]. Rspiwraptimer@10017000,mediatek,mt8186-timermediatek,mt6765-timerMp].scp@10500000mediatek,mt8186-scp MP\ sramcfg]spi@11000000mediatek,mt8186-norM .3OcdRspisfaxiaxi_s^3nX]% disabledadc@11001000.mediatek,mt8186-auxadcmediatek,mt8173-auxadcM."Rmainserial@11002000*mediatek,mt8186-uartmediatek,mt6577-uartM ]p . Rbaudbusokayserial@11003000*mediatek,mt8186-uartmediatek,mt6577-uartM0]q . Rbaudbus disabledi2c@11007000mediatek,mt8186-i2c Mp ]i.' Rmaindma5+okay_defaulti2c@11008000mediatek,mt8186-i2c M ]j.' Rmaindma5+okay_@defaulti2c@11009000mediatek,mt8186-i2c M ]k.' Rmaindma5+okay_'defaulti2c@1100f000mediatek,mt8186-i2c M ]l.' Rmaindma5+okay_defaulti2c@11011000mediatek,mt8186-i2c M ]m.' Rmaindma5+okay_defaulti2c@11016000mediatek,mt8186-i2c M` ]b.' Rmaindma5+okay_defaulti2c@1100d000mediatek,mt8186-i2c M ]c.' Rmaindma5+okay_defaulti2c@11004000mediatek,mt8186-i2c M@ ]n.' Rmaindma5+okay_default i2c@11005000mediatek,mt8186-i2c MP ]o.' Rmaindma5+okay_default!spi@1100a000(mediatek,mt8186-spimediatek,mt6765-spi+M].K Rparent-clksel-clkspi-clk disabledpwm@1100e0002mediatek,mt8186-disp-pwmmediatek,mt8183-disp-pwmM].4Rmainmm disabledspi@11010000(mediatek,mt8186-spimediatek,mt6765-spi+M].K 8Rparent-clksel-clkspi-clk disabledspi@11012000(mediatek,mt8186-spimediatek,mt6765-spi+M ].K ;Rparent-clksel-clkspi-clk disabledspi@11013000(mediatek,mt8186-spimediatek,mt6765-spi+M0].K <Rparent-clksel-clkspi-clk disabledspi@11014000(mediatek,mt8186-spimediatek,mt6765-spi+M@]t.K JRparent-clksel-clkspi-clk disabledspi@11015000(mediatek,mt8186-spimediatek,mt6765-spi+MP]u.K KRparent-clksel-clkspi-clk disabledclock-controller@11017000mediatek,mt8186-imp_iic_wrapMp!serial@11018000*mediatek,mt8186-uartmediatek,mt6577-uartM] . Rbaudbus disabledi2c@11019000mediatek,mt8186-i2c M ]d. ' Rmaindma5+okay_default"mmc@11230000(mediatek,mt8186-mmcmediatek,mt8183-mmc M#. URsourcehclksource_cg]d^ n# disabledmmc@11240000(mediatek,mt8186-mmcmediatek,mt8183-mmc M$.VRsourcehclksource_cg]e^no disabledt-phy@11c80000.mediatek,mt8186-tphymediatek,generic-tphy-v2+hokayusb-phy@0M.Rrefusb-phy@700M .Rreft-phy@11ca0000.mediatek,mt8186-tphymediatek,generic-tphy-v2+hokayusb-phy@0M.Rrefefuse@11cb0000%mediatek,mt8186-efusemediatek,efuseM+dsi-phy@11cc0000mediatek,mt8183-mipi-txM.! Jmipi_tx0_pll disabledclock-controller@13000000mediatek,mt8186-mfgsysM!syscon@14000000mediatek,mt8186-mmsyssysconM!clock-controller@14020000mediatek,mt8186-wpesysM!clock-controller@15020000mediatek,mt8186-imgsys1M!clock-controller@15820000mediatek,mt8186-imgsys2M!clock-controller@1602f000mediatek,mt8186-vdecsysM!clock-controller@17000000mediatek,mt8186-vencsysM!clock-controller@1a000000mediatek,mt8186-camsysM!clock-controller@1a04f000mediatek,mt8186-camsys_rawaM!clock-controller@1a06f000mediatek,mt8186-camsys_rawbM!clock-controller@1b000000mediatek,mt8186-mdpsysM!clock-controller@1c000000mediatek,mt8186-ipesysM!aliases/soc/serial@11002000chosenserial0:921600n8memory@40000000AmemoryM@ compatibleinterrupt-parent#address-cells#size-cellsmodelcpudevice_typeregenable-methodclock-frequencycapacity-dmips-mhzcpu-idle-statesnext-level-cache#cooling-cellsphandleentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-us#clock-cellsclocksclock-divclock-multclock-output-namesinterruptsranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxbias-disabledrive-strength-microampinput-enablebias-pull-upmediatek,disable-extrstclock-namesassigned-clocksassigned-clock-parentsstatus#io-channel-cellspinctrl-namespinctrl-0i2c-scl-internal-delay-ns#pwm-cells#phy-cellsmediatek,discthserial0stdout-path