k8($mediatek,mt8192-evbmediatek,mt8192 +!7MediaTek MT8192 evaluation boardaliases=/soc/ovl@14005000B/soc/ovl@14006000J/soc/ovl@14014000R/soc/rdma@14007000X/soc/rdma@14015000^/soc/serial@11002000fixed-factor-clock-13mfixed-factor-clockfszclk13m#oscillator0 fixed-clockfclk26moscillator1 fixed-clockfclk32kcpus+cpu@0cpuarm,cortex-a55psciec3@ cpu@100cpuarm,cortex-a55psciec3@ cpu@200cpuarm,cortex-a55psciec3@ cpu@300cpuarm,cortex-a55psciec3@ cpu@400cpuarm,cortex-a76pscif cpu@500cpuarm,cortex-a76pscifcpu@600cpuarm,cortex-a76pscifcpu@700cpuarm,cortex-a76pscifcpu-mapcluster0core0 core1 core2 core3 core4 core5 core6 core7 l2-cache0cachel2-cache1cachel3-cachecacheidle-statespscicpu-sleep-larm,idle-state4E7Vf cpu-sleep-barm,idle-state4E#Vfcluster-sleep-larm,idle-state4E<Vf\cluster-sleep-barm,idle-state4E(Vf pmu-a55arm,cortex-a55-pmu wpmu-a76arm,cortex-a76-pmu wpsci arm,psci-1.0smctimerarm,armv8-timer @w   ]@soc+ simple-businterrupt-controller@c000000 arm,gic-v3    w ppi-partitionsinterrupt-partition-0 interrupt-partition-1 syscon@10000000 mediatek,mt8192-topckgensysconfsyscon@10001000 mediatek,mt8192-infracfgsysconfsyscon@10003000mediatek,mt8192-pericfgsyscon0f'pinctrl@10005000mediatek,mt8192-pinctrlP]iocfg0iocfg_rmiocfg_bmiocfg_bliocfg_briocfg_lmiocfg_lbiocfg_rtiocfg_ltiocfg_tleintwsyscon@10006000)mediatek,mt8192-scpsyssysconsimple-mfd`power-controller!mediatek,mt8192-power-controller+)power-domain@0s:/"audioaudio1audio2.power-domain@1s"conn.power-domain@2s"mfg+power-domain@3.+power-domain@4power-domain@5power-domain@6power-domain@7power-domain@8power-domain@9 (s !"dispdisp-0disp-1disp-2disp-3.+power-domain@10 (s"ipeipe-0ipe-1ipe-2ipe-3.power-domain@11 s"ispisp-0isp-1.power-domain@12 s"isp2isp2-0isp2-1.power-domain@13 s "mdpmdp-0.power-domain@14s3 "vencvenc-0.power-domain@15 s4"vdecvdec-0vdec-1vdec-2.+power-domain@16s"vdec2-0vdec2-1vdec2-2power-domain@17(s "camcam-0cam-1cam-2cam-3.+power-domain@18s  "cam_rawa-0power-domain@19s! "cam_rawb-0power-domain@20s" "cam_rawc-0watchdog@10007000mediatek,mt8192-wdtp(syscon@1000c000"mediatek,mt8192-apmixedsyssysconf&timer@10017000,mediatek,mt8192-timermediatek,mt6765-timerpws#pwrap@10026000mediatek,mt6873-pwrap`pwrapws "spiwrap@Ppmicmediatek,mt6359mt6359codecregulatorsbuck_vs1gvs1v 5!buck_vgpu11gvgpu11v7 buck_vmodemgvmodemv*buck_vpugvpuv7 buck_vcoregvcorev  buck_vs2gvs2v 5jbuck_vpagvpav 7,buck_vproc2gvproc2v7L buck_vproc1gvproc1v7L buck_vcore_sshub gvcore_sshubv7buck_vgpu11_sshub gvgpu11_sshubv7ldo_vaud18gvaud18vw@w@ldo_vsim1gvsim1v/M`ldo_vibrgvibrvO2Zldo_vrf12gvrf12v ldo_vusbgvusbv--ldo_vsram_proc2 gvsram_proc2v Lldo_vio18gvio18vldo_vcamiogvcamiovldo_vcn18gvcn18vw@w@ldo_vfe28gvfe28v**xldo_vcn13gvcn13v  ldo_vcn33_1_bt gvcn33_1_btv*5gldo_vcn33_1_wifi gvcn33_1_wifiv*5gldo_vaux18gvaux18vw@w@ldo_vsram_others gvsram_othersv ldo_vefusegvefusevldo_vxo22gvxo22vw@!ldo_vrfckgvrfckv`ldo_vrfck_1gvrfckvjldo_vbif28gvbif28v**ldo_vio28gvio28v*2Zldo_vemcgvemcv,@ 2Zldo_vemc_1gvemcv&%2Zldo_vcn33_2_bt gvcn33_2_btv*5gldo_vcn33_2_wifi gvcn33_2_wifiv*5gldo_va12gva12vO ldo_va09gva09v 5Oldo_vrf18gvrf18vPldo_vsram_md gvsram_mdv *ldo_vufsgvufsvldo_vm18gvm18vldo_vbbckgvbbckvOldo_vsram_proc1 gvsram_proc1v Lldo_vsim2gvsim2v/M`ldo_vsram_others_sshubgvsram_others_sshubv mt6359rtcmediatek,mt6358-rtcspmi@10027000mediatek,mt6873-spmi p pmifspmimsts8("pmif_sys_ckpmif_tmr_ckspmimst_clk_mux@Pmailbox@10228000mediatek,mt8192-gce"@ws"gce2clock-controller@10720000mediatek,mt8192-scp_adsprffailserial@11002000*mediatek,mt8192-uartmediatek,mt6577-uart wm s "baudbusokayserial@11003000*mediatek,mt8192-uartmediatek,mt6577-uart0wn s "baudbus disabledclock-controller@11007000mediatek,mt8192-imp_iic_wrap_cpfspi@1100a000(mediatek,mt8192-spimediatek,mt6765-spi+wsM"parent-clksel-clkspi-clk disabledpwm@1100e000mediatek,mt8183-disp-pwmws!8"mainmm disabledspi@11010000(mediatek,mt8192-spimediatek,mt6765-spi+wsM<"parent-clksel-clkspi-clk disabledspi@11012000(mediatek,mt8192-spimediatek,mt6765-spi+ wsM>"parent-clksel-clkspi-clk disabledspi@11013000(mediatek,mt8192-spimediatek,mt6765-spi+0wsM?"parent-clksel-clkspi-clk disabledspi@11018000(mediatek,mt8192-spimediatek,mt6765-spi+wsML"parent-clksel-clkspi-clk disabledspi@11019000(mediatek,mt8192-spimediatek,mt6765-spi+wsMM"parent-clksel-clkspi-clk disabledspi@1101d000(mediatek,mt8192-spimediatek,mt6765-spi+wsMm"parent-clksel-clkspi-clk disabledspi@1101e000(mediatek,mt8192-spimediatek,mt6765-spi+wsMn"parent-clksel-clkspi-clk disabledscp@10500000mediatek,mt8192-scp0Prpsramcfgl1tcmws"main disabledEusb@11200000'mediatek,mt8192-xhcimediatek,mtk-xhci   > macippc!a5hostE$%@"#P]] s7&R$"sys_ckref_ckmcu_ckdma_ckxhci_ckJ X' f disabledsyscon@11210000mediatek,mt8192-audsyssyscon! f*mt8192-afe-pcmmediatek,mt8192-audiowo( vaudiosys&.)s*********** * ********/:H/e0i+g,k;<=>?@ABCD7u"aud_afe_clkaud_dac_clkaud_dac_predis_clkaud_adc_clkaud_adda6_adc_clkaud_apll22m_clkaud_apll24m_clkaud_apll1_tuner_clkaud_apll2_tuner_clkaud_tdm_clkaud_tml_clkaud_nleaud_dac_hires_clkaud_adc_hires_clkaud_adc_hires_tmlaud_adda6_adc_hires_clkaud_3rd_dac_clkaud_3rd_dac_predis_clkaud_3rd_dac_tmlaud_3rd_dac_hires_clkaud_infra_clkaud_infra_26m_clktop_mux_audiotop_mux_audio_inttop_mainpll_d4_d4top_mux_aud_1top_apll1_cktop_mux_aud_2top_apll2_cktop_mux_aud_eng1top_apll1_d4top_mux_aud_eng2top_apll2_d4top_i2s0_m_seltop_i2s1_m_seltop_i2s2_m_seltop_i2s3_m_seltop_i2s4_m_seltop_i2s5_m_seltop_i2s6_m_seltop_i2s7_m_seltop_i2s8_m_seltop_i2s9_m_seltop_apll12_div0top_apll12_div1top_apll12_div2top_apll12_div3top_apll12_div4top_apll12_divbtop_apll12_div5top_apll12_div6top_apll12_div7top_apll12_div8top_apll12_div9top_mux_audio_htop_clk26m_clkpcie@11230000mediatek,mt8192-pciepci#  pcie-mac+0s+'*j^\/"pl_250mtl_26mtl_96mtl_32kperi_26mtop_133m@)PQw8`++++interrupt-controller+spi@11234000mediatek,mt8192-nor#@ws:w] "spisfaxi@:P+ disabledefuse@11c10000%mediatek,mt8192-efusemediatek,efuse+data1@1c0Xcalib@580hi2c@11cb0000mediatek,mt8192-i2c !swss,x "maindmaz+ disabledclock-controller@11cb1000mediatek,mt8192-imp_iic_wrap_ef,i2c@11d00000mediatek,mt8192-i2c !vwws-x "maindmaz+ disabledi2c@11d01000mediatek,mt8192-i2c !wwxs-x "maindmaz+ disabledi2c@11d02000mediatek,mt8192-i2c  !ywys-x "maindmaz+ disabledclock-controller@11d03000mediatek,mt8192-imp_iic_wrap_s0f-i2c@11d20000mediatek,mt8192-i2c !qwqs.x "maindmaz+ disabledi2c@11d21000mediatek,mt8192-i2c !qwrs.x "maindmaz+ disabledi2c@11d22000mediatek,mt8192-i2c  !swts.x "maindmaz+ disabledclock-controller@11d23000 mediatek,mt8192-imp_iic_wrap_ws0f.i2c@11e00000mediatek,mt8192-i2c !uwus/x "maindmaz+ disabledclock-controller@11e01000mediatek,mt8192-imp_iic_wrap_wf/t-phy@11e40000.mediatek,mt8192-tphymediatek,generic-tphy-v2+usb-phy@0s"ref$usb-phy@700 s"ref%dsi-phy@11e50000mediatek,mt8183-mipi-txs& f mipi_tx0_pll disabled5i2c@11f00000mediatek,mt8192-i2c !pwps0x "maindmaz+ disabledi2c@11f01000mediatek,mt8192-i2c !uwvs0x "maindmaz+ disabledclock-controller@11f02000mediatek,mt8192-imp_iic_wrap_n f0clock-controller@11f10000mediatek,mt8192-msdc_topf1mmc@11f60000(mediatek,mt8192-mmcmediatek,mt8183-mmc wc8s1 111113"sourcehclksource_cgsys_cgpclk_cgaxi_cgahb_cg disabledmmc@11f70000(mediatek,mt8192-mmcmediatek,mt8183-mmc wg8s1 111113"sourcehclksource_cgsys_cgpclk_cgaxi_cgahb_cg disabledclock-controller@13fbf000mediatek,mt8192-mfgcfgfsyscon@14000000mediatek,mt8192-mmsyssysconf222mutex@14001000mediatek,mt8192-disp-mutexws ) smi@14002000mediatek,mt8192-smi-common  s "apbsmigals0gals1) 3larb@14003000mediatek,mt8192-smi-larb003s"apbsmi) 6larb@14004000mediatek,mt8192-smi-larb@03s"apbsmi) 7ovl@14005000mediatek,mt8192-disp-ovlPws=44) 2Povl@14006000mediatek,mt8192-disp-ovl-2l`w) s=4"4 2`rdma@140070004mediatek,mt8192-disp-rdmamediatek,mt8183-disp-rdmapws=4D) 2pcolor@140090006mediatek,mt8192-disp-colormediatek,mt8173-disp-colorw) s2ccorr@1400a000mediatek,mt8192-disp-ccorrw) s 2aal@1400b0002mediatek,mt8192-disp-aalmediatek,mt8183-disp-aalw) s2gamma@1400c0006mediatek,mt8192-disp-gammamediatek,mt8183-disp-gammaw) s 2postmask@1400d000mediatek,mt8192-disp-postmaskw) s 2dither@1400e0008mediatek,mt8192-disp-dithermediatek,mt8183-disp-ditherw) s 2dsi@14010000mediatek,mt8183-dsiw s 5"enginedigitalhsE5\dphy) o disabledportendpointovl@14014000mediatek,mt8192-disp-ovl-2l@w ) s=4#4!2@rdma@140150004mediatek,mt8192-disp-rdmamediatek,mt8183-disp-rdmaPw ) s=4%D2Pdpi@14016000mediatek,mt8192-dpi`ws!&"pixelenginepll disabledm4u@1401d000mediatek,mt8192-m4u<f6789:;<=>?@ABCDws"bclk) u4clock-controller@15020000mediatek,mt8192-imgsysflarb@1502e000mediatek,mt8192-smi-larb 03s"apbsmi) <clock-controller@15820000mediatek,mt8192-imgsys2flarb@1582e000mediatek,mt8192-smi-larb 03s"apbsmi) =larb@1600d000mediatek,mt8192-smi-larb03s"apbsmi):clock-controller@1600f000mediatek,mt8192-vdecsys_socflarb@1602e000mediatek,mt8192-smi-larb03s"apbsmi)9clock-controller@1602f000mediatek,mt8192-vdecsysfclock-controller@17000000mediatek,mt8192-vencsysflarb@17010000mediatek,mt8192-smi-larb03s"apbsmi);vcodec@17020000mediatek,mt8192-vcodec-enc X=44444444444w5E)s "venc-set1@3PWclock-controller@1a000000mediatek,mt8192-camsysflarb@1a001000mediatek,mt8192-smi-larb 03s"apbsmi)>larb@1a002000mediatek,mt8192-smi-larb 03s"apbsmi)?larb@1a00f000mediatek,mt8192-smi-larb03s  "apbsmi)@larb@1a010000mediatek,mt8192-smi-larb03s!!"apbsmi)Alarb@1a011000mediatek,mt8192-smi-larb03s"""apbsmi)Bclock-controller@1a04f000mediatek,mt8192-camsys_rawaf clock-controller@1a06f000mediatek,mt8192-camsys_rawbf!clock-controller@1a08f000mediatek,mt8192-camsys_rawcf"clock-controller@1b000000mediatek,mt8192-ipesysflarb@1b00f000mediatek,mt8192-smi-larb03s"apbsmi) Dlarb@1b10f000mediatek,mt8192-smi-larb03s"apbsmi) Cclock-controller@1f000000mediatek,mt8192-mdpsysflarb@1f002000mediatek,mt8192-smi-larb 03s"apbsmi) 8chosenserial0:921600n8memory@40000000memory@ compatibleinterrupt-parent#address-cells#size-cellsmodelovl0ovl-2l0ovl-2l2rdma0rdma4serial0#clock-cellsclocksclock-divclock-multclock-output-namesphandleclock-frequencydevice_typeregenable-methodcpu-idle-statesnext-level-cachecapacity-dmips-mhzcpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usinterruptsranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-ranges#power-domain-cellsclock-namesmediatek,infracfgassigned-clocksassigned-clock-parentsregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modes#mbox-cellsstatus#pwm-cellsinterrupts-extendedinterrupt-namesphyswakeup-sourcemediatek,syscon-wakeupresetsreset-namesmediatek,apmixedsysmediatek,topckgenpower-domainsbus-rangeinterrupt-map-maskinterrupt-map#phy-cellsmboxesmediatek,gce-client-regmediatek,gce-eventsmediatek,larb-idmediatek,smiiommusmediatek,rdma-fifo-sizephy-namesmediatek,larbs#iommu-cellsmediatek,scpstdout-path