G8Ѩ(p1google,tomato-rev2google,tomatomediatek,mt8195 +7Acer Tomato (rev2) boardaliases=/soc/mailbox@10320000B/soc/mailbox@10330000G/soc/i2c@11e00000L/soc/i2c@11e01000Q/soc/i2c@11e02000V/soc/i2c@11e03000[/soc/i2c@11e04000`/soc/i2c@11d00000e/soc/i2c@11d02000j/soc/mmc@11230000o/soc/mmc@11240000t/soc/serial@11001100cpus+cpu@0|cpuarm,cortex-a55psciec3@4 cpu@100|cpuarm,cortex-a55psciec3@4 cpu@200|cpuarm,cortex-a55psciec3@4 cpu@300|cpuarm,cortex-a55psciec3@4 cpu@400|cpuarm,cortex-a78pscif cpu@500|cpuarm,cortex-a78pscifcpu@600|cpuarm,cortex-a78pscifcpu@700|cpuarm,cortex-a78pscifcpu-mapcluster0core0 core1 core2 core3 core4 core5 core6 core7 idle-states pscicpu-off-larm,idle-state1B2S_cDcpu-off-barm,idle-state1B-Sccluster-off-larm,idle-state1B7ScHcluster-off-barm,idle-state1B2Scl2-cache0cachel2-cache1cachel3-cachecachedsu-pmu arm,dsu-pmut  dmic-codec dmic-codec2mt8195-sound disabledfixed-factor-clock-13mfixed-factor-clockclk13m'oscillator-26m fixed-clockclk26moscillator-32k fixed-clockclk32kperformance-controller@11bc10mediatek,cpufreq-hw  0 pmu-a55arm,cortex-a55-pmu tpmu-a78arm,cortex-a78-pmu tpsci arm,psci-1.0smctimerarm,armv8-timer @t   soc+ simple-businterrupt-controller@c000000 arm,gic-v3( ?   t ppi-partitionsinterrupt-partition-0T interrupt-partition-1T syscon@10000000 mediatek,mt8195-topckgensysconsyscon@10001000.mediatek,mt8195-infracfg_aosysconsimple-mfd]syscon@10003000mediatek,mt8195-pericfgsyscon03pinctrl@10005000mediatek,mt8195-pinctrlPBjiocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleintt?tdefault>I2S_SPKR_MCLKI2S_SPKR_DATAINI2S_SPKR_LRCKI2S_SPKR_BCLKEC_AP_INT_ODLAP_FLASH_WP_LTCHPAD_INT_ODLEDP_HPD_1V8AP_I2C_CAM_SDAAP_I2C_CAM_SCLAP_I2C_TCHPAD_SDA_1V8AP_I2C_TCHPAD_SCL_1V8AP_I2C_AUD_SDAAP_I2C_AUD_SCLAP_I2C_TPM_SDA_1V8AP_I2C_TPM_SCL_1V8AP_I2C_TCHSCR_SDA_1V8AP_I2C_TCHSCR_SCL_1V8EC_AP_HPD_ODPCIE_NVME_RST_LPCIE_NVME_CLKREQ_ODLPCIE_RST_1V8_LPCIE_CLKREQ_1V8_ODLPCIE_WAKE_1V8_ODLCLK_24M_CAM0CAM1_SEN_ENAP_I2C_PWR_SCL_1V8AP_I2C_PWR_SDA_1V8AP_I2C_MISC_SCLAP_I2C_MISC_SDAEN_PP5000_HDMI_XAP_HDMITX_HTPLGAP_HDMITX_SCL_1V8AP_HDMITX_SDA_1V8AP_RTC_CLK32KAP_EC_WATCHDOG_LSRCLKENA0SRCLKENA1PWRAP_SPI0_CS_LPWRAP_SPI0_CKPWRAP_SPI0_MOSIPWRAP_SPI0_MISOSPMI_SCLSPMI_SDAI2S_HP_DATAINI2S_HP_MCLKI2S_HP_BCKI2S_HP_LRCKI2S_HP_DATAOUTSD_CD_ODLEN_PP3300_DISP_XTCHSCR_RST_1V8_LTCHSCR_REPORT_DISABLEEN_PP3300_WLAN_XBT_KILL_1V8_LI2S_SPKR_DATAOUTWIFI_KILL_1V8_LBEEP_ONSCP_I2C_SENSOR_SCL_1V8SCP_I2C_SENSOR_SDA_1V8AUD_CLK_MOSIAUD_SYNC_MOSIAUD_DAT_MOSI0AUD_DAT_MOSI1AUD_DAT_MISO0AUD_DAT_MISO1AUD_DAT_MISO2SCP_VREQ_VAOAP_SPI_GSC_TPM_CLKAP_SPI_GSC_TPM_MOSIAP_SPI_GSC_TPM_CS_LAP_SPI_GSC_TPM_MISOEN_PP1000_CAM_XAP_EDP_BKLTENUSB3_HUB_RST_LWLAN_ALERT_ODLEC_IN_RW_ODLGSC_AP_INT_ODLHP_INT_ODLCAM0_RST_LCAM1_RST_LTCHSCR_INT_1V8_LCAM1_DET_LRST_ALC1011_LBL_PWM_1V8UART_AP_TX_DBG_RXUART_DBG_TX_AP_RXEN_SPKRAP_EC_WARM_RST_REQUART_SCP_TX_DBGCON_RXUART_DBGCON_TX_SCP_RXKPCOL0MT6315_GPU_INTMT6315_PROC_BC_INTSD_CMDSD_CLKSD_DAT0SD_DAT1SD_DAT2SD_DAT3EMMC_DAT7EMMC_DAT6EMMC_DAT5EMMC_DAT4EMMC_RSTBEMMC_CMDEMMC_CLKEMMC_DAT3EMMC_DAT2EMMC_DAT1EMMC_DAT0EMMC_DSLMT6360_INT_ODLSCP_JTAG0_TRSTNAP_SPI_EC_CS_LAP_SPI_EC_CLKAP_SPI_EC_MOSIAP_SPI_EC_MISOSCP_JTAG0_TMSSCP_JTAG0_TCKSCP_JTAG0_TDOSCP_JTAG0_TDIAP_SPI_FLASH_CS_LAP_SPI_FLASH_CLKAP_SPI_FLASH_MOSIAP_SPI_FLASH_MISOcr50-irq-default-pinsMpins-gsc-ap-int-odlXcros-ec-irq-default-pins0pins-ec-ap-int-odlei2c0-default-pinsGpins-bus  i2c1-default-pinsHpins-bus  i2c2-default-pinsKpins-bus   i2c3-default-pinsLpins-busi2c4-default-pinsNpins-bus.i2c5-default-pinsCpins-bus i2c7-default-pinsDpins-bus mmc0-default-pins6pins-cmd-dat$~}|{wvuty.epins-clkz.=fpins-rstx.emmc0-uhs-pins7pins-cmd-dat$~}|{wvuty.epins-clkz.=fpins-ds.=fpins-rstx.emmc1-detect-pins;pins-insert6mmc1-default-pins:pins-cmd-datnpqrs.epins-clko.=fnor-default-pinsApins-ck-io .=pins-cs.pio-default-pinspins-wifi-enable:L.pins-low-power-pd,./0ABCD=pins-low-power-pupd<MNOPSUZ[]^_`hik=epins-low-power-hdmi-disable !"#=pins-low-power-pcie0-disable =scp-default-pins)pins-vreqL spi0-default-pins/pins-cs-mosi-clk  pins-miso=subpmic-default-pinsEpins-subpmic-int-ntrackpad-default-pinsIpins-int-ntouchscreen-default-pinsOpins-int-n\epins-rst8Lpins-report-sw9Xsyscon@10006000)mediatek,mt8195-scpsyssysconsimple-mfd`power-controller!mediatek,mt8195-power-controller+c+power-domain@8+cpower-domain@9 wmfg+cpower-domain@10 cpower-domain@11 cpower-domain@12 cpower-domain@13 cpower-domain@14cpower-domain@15 @AK   wvppsysvppsys1vppsys2vppsys3vppsys4vppsys5vppsys6vppsys7vppsys0-0vppsys0-1vppsys0-2vppsys0-3vppsys0-4vppsys0-5vppsys0-6vppsys0-7vppsys0-8vppsys0-9vppsys0-10vppsys0-11vppsys0-12vppsys0-13vppsys0-14vppsys0-15vppsys0-16vppsys0-17vppsys0-18+cpower-domain@24wvdec1-0cpower-domain@27cpower-domain@168$%&'()Dwvdosys0vdosys0-0vdosys0-1vdosys0-2vdosys0-3vdosys0-4vdosys0-5+cpower-domain@17wvppsys1vppsys1-0vppsys1-1cpower-domain@22 $wwepsys-0wepsys-1wepsys-2wepsys-3cpower-domain@23 wvdec0-0cpower-domain@25!wvdec2-0cpower-domain@26cpower-domain@18 """&wvdosys1vdosys1-0vdosys1-1vdosys1-2+cpower-domain@19cpower-domain@20cpower-domain@21Qwhdmi_txcpower-domain@28##  wimg-0img-1+cpower-domain@29cpower-domain@30#$wipeipe-0ipe-1cpower-domain@31(%%%%%wcam-0cam-1cam-2cam-3cam-4+cpower-domain@32 cpower-domain@33!cpower-domain@34"cpower-domain@0cpower-domain@1cpower-domain@2cpower-domain@3cpower-domain@457wcsi_rx_topcsi_rx_top1cpower-domain@5& wethercpower-domain@6Xn wadspadsp1+cpower-domain@7 g"n2waudioaudio1audio2audio3cwatchdog@10007000mediatek,mt8195-wdtp].syscon@1000c000"mediatek,mt8195-apmixedsyssyscontimer@10017000,mediatek,mt8195-timermediatek,mt6765-timerpt 'pwrap@10024000mediatek,mt8195-pwrapsyscon@jpwrapt wspiwrap$pmicmediatek,mt6359? mt6359codecregulatorsbuck_vs1vs1 5!'Cbuck_vgpu11vgpu117W' lCbuck_vmodemvmodemW*'buck_vpuvpu7W' lCbuck_vcorevcore W' lCbuck_vs2vs2 5j'Cbuck_vpavpa 7',buck_vproc2vproc27WL' lbuck_vproc1vproc17WL' lbuck_vcore_sshub vcore_sshub7buck_vgpu11_sshub vgpu11_sshubdpdpCldo_vaud18vaud18w@w@'ldo_vsim1vsim1/M`ldo_vibrvibrO2Zldo_vrf12vrf12 Cldo_vusbvusb--'C4ldo_vsram_proc2 vsram_proc2 WL'Cldo_vio18vio18'Cldo_vcamiovcamioldo_vcn18vcn18w@w@'ldo_vfe28vfe28**'xldo_vcn13vcn13  ldo_vcn33_1_bt vcn33_1_bt*5gldo_vcn33_1_wifi vcn33_1_wifi*5gldo_vaux18vaux18w@w@'Cldo_vsram_others vsram_others q qW'Cldo_vefusevefuseldo_vxo22vxo22w@!Cldo_vrfckvrfck`ldo_vrfck_1vrfckjldo_vbif28vbif28**'ldo_vio28vio28*2ZCldo_vemcvemc,@ 2Zldo_vemc_1vemc&%2Z8ldo_vcn33_2_bt vcn33_2_bt*5gldo_vcn33_2_wifi vcn33_2_wifi*5gldo_va12va12O Cldo_va09va09 5Oldo_vrf18vrf18Pldo_vsram_md vsram_md W*'ldo_vufsvufsC9ldo_vm18vm18Cldo_vbbckvbbckOldo_vsram_proc1 vsram_proc1 WL'Cldo_vsim2vsim2/M`ldo_vsram_others_sshubvsram_others_sshub mt6359rtcmediatek,mt6358-rtcspmi@10027000mediatek,mt8195-spmi p jpmifspmimstE(wpmif_sys_ckpmif_tmr_ckspmimst_clk_mux$+mt6315@6mediatek,mt6315-regulatorregulatorsvbuck1vbuck1Vbcpu7'Wj lCmt6315@7mediatek,mt6315-regulatorregulatorsvbuck1vbuck1Vgpu h7'Wj lCinfra-iommu@10315000mediatek,mt8195-iommu-infra1PPPtmailbox@10320000mediatek,mt8195-gce2@tumailbox@10330000mediatek,mt8195-gce3@tscp@10500000mediatek,mt8195-scp0Prpjsramcfgl1tcmtokaymediatek/mt8195/scp.img(default)cros-ec-rpmsggoogle,cros-ec-rpmsgcros-ec-rpmsgclock-controller@10720000mediatek,mt8195-scp_adspr*dsp@10803000mediatek,mt8195-dsp 0 jcfgsram,Xn*#Kwadsp_selclk26m_ckaudio_local_busmainpll_d7_d2scp_adsp_audiodspaudio_h+rxtx,- disabledmailbox@10816000mediatek,mt8195-adsp-mbox`t,mailbox@10817000mediatek,mt8195-adsp-mboxpt-mt8195-afe-pcm@10890000mediatek,mt8195-audio+t6. audiosysg"#neabcd2*wclk26mapll1_ckapll2_ckapll12_div0apll12_div1apll12_div2apll12_div3apll12_div9a1sys_hp_selaud_intbus_selaudio_h_selaudio_local_bus_seldptx_m_seli2so1_m_seli2so2_m_seli2si1_m_seli2si2_m_selinfra_ao_audio_26m_bscp_adsp_audiodsp disabledserial@11001100*mediatek,mt8195-uartmediatek,mt6577-uartt  wbaudbusokayserial@11001200*mediatek,mt8195-uartmediatek,mt6577-uartt  wbaudbus disabledserial@11001300*mediatek,mt8195-uartmediatek,mt6577-uartt  wbaudbus disabledserial@11001400*mediatek,mt8195-uartmediatek,mt6577-uartt  wbaudbus disabledserial@11001500*mediatek,mt8195-uartmediatek,mt6577-uartt  wbaudbus disabledserial@11001600*mediatek,mt8195-uartmediatek,mt6577-uartt  wbaudbus disabledauxadc@11002000.mediatek,mt8195-auxadcmediatek,mt8173-auxadc wmain' disabledsyscon@11003000"mediatek,mt8195-pericfg_aosyscon0&spi@1100a000(mediatek,mt8195-spimediatek,mt6765-spi+twparent-clksel-clkspi-clkokaydefault/9ec@0+google,cros-ec-spi default0M-keyboard-backlightgoogle,cros-kbd-led-backlighti2c-tunnelgoogle,cros-ec-i2c-tunnel_+sbs-battery@bsbs,sbs-battery qregulator@0google,cros-ec-regulatormt_pmic_vmc_ldoO6=regulator@1google,cros-ec-regulatormt_pmic_vmch_ldo)26<typecgoogle,cros-ec-typec+connector@0usb-c-connectordualhostsourceconnector@1usb-c-connectordualhostsourcekeyboard-controllergoogle,cros-ec-keyb Dtxc q rs}0Y1 d"#(  \V |})   + ^a !%$' & + ,./-32*5 4 9    8 l j6  g i(  spi@11010000(mediatek,mt8195-spimediatek,mt6765-spi+t3wparent-clksel-clkspi-clk disabledspi@11012000(mediatek,mt8195-spimediatek,mt6765-spi+ t4wparent-clksel-clkspi-clk disabledspi@11013000(mediatek,mt8195-spimediatek,mt6765-spi+0t5wparent-clksel-clkspi-clk disabledspi@11018000(mediatek,mt8195-spimediatek,mt6765-spi+t<wparent-clksel-clkspi-clk disabledspi@11019000(mediatek,mt8195-spimediatek,mt6765-spi+t=wparent-clksel-clkspi-clk disabledspi@1101d000mediatek,mt8195-spi-slavetRwspi disabledspi@1101e000mediatek,mt8195-spi-slavetSwspi disabledusb@11200000'mediatek,mt8195-xhcimediatek,mtk-xhci   > jmacippct12,-$/B$wsys_ckref_ckmcu_ckdma_ckxhci_ck "3g9okayG4U5mmc@11230000(mediatek,mt8195-mmcmediatek,mt8183-mmc #twsourcehclksource_cgokayak}LQ defaultstate_uhs6789mmc@11240000(mediatek,mt8195-mmcmediatek,mt8183-mmc $t$wsourcehclksource_cgokaya  6Q defaultstate_uhs:;:(<=mmc@11250000(mediatek,mt8195-mmcmediatek,mt8183-mmc %t Iwsourcehclksource_cg  disabledusb@11290000'mediatek,mt8195-xhcimediatek,mtk-xhci ))> jmacippct>./$&&$wsys_ckref_ckmcu_ckdma_ckxhci_ck "3h9okayG4U5usb@112a0000'mediatek,mt8195-xhcimediatek,mtk-xhci **> jmacippct?01 &&$wsys_ckref_ckmcu_ckdma_ckxhci_ck "3i9okayG4U5usb@112b0000'mediatek,mt8195-xhcimediatek,mtk-xhci ++> jmacippct@23 && $wsys_ckref_ckmcu_ckdma_ckxhci_ck "3j9okay6G4U5spi@1132c000(mediatek,mt8195-normediatek,mt8173-nor2t9o&& wspisfaxi+okaydefaultAflash@0jedec,spi-norMuGXefuse@11c10000%mediatek,mt8195-efusemediatek,efuse+usb3-tx-imp@184,1iUusb3-rx-imp@184,2iTusb3-intr@185iSusb3-tx-imp@186,1iRusb3-rx-imp@186,2iQusb3-intr@187iPusb2-intr-p0@188,1iusb2-intr-p1@188,2iusb2-intr-p2@189,1iusb2-intr-p3@189,2it-phy@11c40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+okayusb-phy@0wrefn?t-phy@11c50000.mediatek,mt8195-tphymediatek,generic-tphy-v3+okayusb-phy@0wrefn@i2c@11d00000(mediatek,mt8195-i2cmediatek,mt8192-i2c "tB; wmaindma+okaydefaultCi2c@11d01000(mediatek,mt8195-i2cmediatek,mt8192-i2c "tB; wmaindma+ disabledi2c@11d02000(mediatek,mt8195-i2cmediatek,mt8192-i2c  "tB; wmaindma+okaydefaultDpmic@34mediatek,mt63604? yIRQBdefaultE9clock-controller@11d03000mediatek,mt8195-imp_iic_wrap_s0Bi2c@11e00000(mediatek,mt8195-i2cmediatek,mt8192-i2c "tF; wmaindma+okaydefaultGi2c@11e01000(mediatek,mt8195-i2cmediatek,mt8192-i2c "tF; wmaindma+okay0defaultHtrackpad@15elan,ekth3000 defaultIJ9i2c@11e02000(mediatek,mt8195-i2cmediatek,mt8192-i2c  "tF; wmaindma+okaydefaultKi2c@11e03000(mediatek,mt8195-i2cmediatek,mt8192-i2c 0"tF; wmaindma+okaydefaultLtpm@50 google,cr50P XdefaultMi2c@11e04000(mediatek,mt8195-i2cmediatek,mt8192-i2c @"tF; wmaindma+okaydefaultNtouchscreen@10 hid-over-i2c \defaultO Jokayclock-controller@11e05000mediatek,mt8195-imp_iic_wrap_wPFt-phy@11e30000.mediatek,mt8195-tphymediatek,generic-tphy-v3++okayusb-phy@0  wrefda_refn>usb-phy@700 wrefda_ref PQRintrrx_imptx_impnt-phy@11e40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+okayusb-phy@0  wrefda_refn1usb-phy@700 wrefda_ref STUintrrx_imptx_impn2ufs-phy@11fa0000.mediatek,mt8195-ufsphymediatek,mt8183-ufsphy wuniprompn disabledclock-controller@13fbf000mediatek,mt8195-mfgcfgclock-controller@14000000mediatek,mt8195-vppsys0smi@14010000mediatek,mt8195-smi-sub-commonwapbsmigals0V+Wsmi@14011000mediatek,mt8195-smi-sub-commonwapbsmigals0V+ssmi@14012000mediatek,mt8195-smi-common-vpp  wapbsmigals0gals1+Vlarb@14013000mediatek,mt8195-smi-larb0 Wwapbsmi+Ziommu@14018000mediatek,mt8195-iommu-vpp8XYZ[\]^_`abcdetRwbclk+clock-controller@14e00000mediatek,mt8195-wpesysclock-controller@14e02000mediatek,mt8195-wpesys_vpp0 clock-controller@14e03000mediatek,mt8195-wpesys_vpp10larb@14e04000mediatek,mt8195-smi-larb@ fwapbsmi+{larb@14e05000mediatek,mt8195-smi-larbP V wapbsmigals+\clock-controller@14f00000mediatek,mt8195-vppsys1larb@14f02000mediatek,mt8195-smi-larb  f wapbsmigals+zlarb@14f03000mediatek,mt8195-smi-larb0 W wapbsmigals+[clock-controller@15000000mediatek,mt8195-imgsys#larb@15001000mediatek,mt8195-smi-larb g###  wapbsmigals+|smi@15002000mediatek,mt8195-smi-sub-common ##wapbsmigals0V+jsmi@15003000mediatek,mt8195-smi-sub-common0### wapbsmigals0f+gclock-controller@15110000 mediatek,mt8195-imgsys1_dip_tophlarb@15120000mediatek,mt8195-smi-larb g#hwapbsmi+}clock-controller@15130000mediatek,mt8195-imgsys1_dip_nrclock-controller@15220000mediatek,mt8195-imgsys1_wpe"ilarb@15230000mediatek,mt8195-smi-larb# g#iwapbsmi+~clock-controller@15330000mediatek,mt8195-ipesys3$larb@15340000mediatek,mt8195-smi-larb4 j$$wapbsmi+]clock-controller@16000000mediatek,mt8195-camsys%larb@16001000mediatek,mt8195-smi-larb k%%% wapbsmigals+larb@16002000mediatek,mt8195-smi-larb  l%%wapbsmi+^smi@16004000mediatek,mt8195-smi-sub-common@%%%wapbsmigals0f+ksmi@16005000mediatek,mt8195-smi-sub-commonP%%wapbsmigals0V+llarb@16012000mediatek,mt8195-smi-larb  lmmwapbsmi+ _larb@16013000mediatek,mt8195-smi-larb0 knnwapbsmi+ larb@16014000mediatek,mt8195-smi-larb@ loowapbsmi+!elarb@16015000mediatek,mt8195-smi-larbP kppwapbsmi+!clock-controller@1604f000mediatek,mt8195-camsys_rawamclock-controller@1606f000mediatek,mt8195-camsys_yuvanclock-controller@1608f000mediatek,mt8195-camsys_rawboclock-controller@160af000mediatek,mt8195-camsys_yuvb pclock-controller@16140000mediatek,mt8195-camsys_mrawqlarb@16141000mediatek,mt8195-smi-larb k%q% wapbsmigals+"larb@16142000mediatek,mt8195-smi-larb  lqqwapbsmi+"dclock-controller@17200000mediatek,mt8195-ccusys rlarb@17201000mediatek,mt8195-smi-larb  lrrwapbsmi+`larb@1800d000mediatek,mt8195-smi-larb f wapbsmi+larb@1800e000mediatek,mt8195-smi-larb s wapbsmi+cclock-controller@1800f000mediatek,mt8195-vdecsys_soc larb@1802e000mediatek,mt8195-smi-larb fwapbsmi+clock-controller@1802f000mediatek,mt8195-vdecsyslarb@1803e000mediatek,mt8195-smi-larb s!wapbsmi+bclock-controller@1803f000mediatek,mt8195-vdecsys_core1!clock-controller@190f3000mediatek,mt8195-apusys_pll0clock-controller@1a000000mediatek,mt8195-vencsystlarb@1a010000mediatek,mt8195-smi-larb fttwapbsmi+clock-controller@1b000000mediatek,mt8195-vencsys_core1vsyscon@1c01a0005mediatek,mt8195-vdosys0mediatek,mt8195-mmsyssyscon ularb@1b010000mediatek,mt8195-smi-larb Vvv  wapbsmigals+aovl@1c0000002mediatek,mt8195-disp-ovlmediatek,mt8183-disp-ovlt|+)w0urdma@1c002000mediatek,mt8195-disp-rdma t~+)w0u color@1c0030006mediatek,mt8195-disp-colormediatek,mt8173-disp-color0t+0u0ccorr@1c0040006mediatek,mt8195-disp-ccorrmediatek,mt8192-disp-ccorr@t+0u@aal@1c0050002mediatek,mt8195-disp-aalmediatek,mt8183-disp-aalPt+0uPgamma@1c0060006mediatek,mt8195-disp-gammamediatek,mt8183-disp-gamma`t+0u`dither@1c0070008mediatek,mt8195-disp-dithermediatek,mt8183-disp-ditherpt+ 0updsc@1c009000mediatek,mt8195-disp-dsct+0umerge@1c014000mediatek,mt8195-disp-merge@t+0u@mutex@1c016000mediatek,mt8195-disp-mutex`t+HUlarb@1c018000mediatek,mt8195-smi-larb f((  wapbsmigals+xlarb@1c019000mediatek,mt8195-smi-larb V(  wapbsmigals+Xsyscon@1c100000mediatek,mt8195-vdosys1syscon"smi@1c01b000mediatek,mt8195-smi-common-vdo %&)$wapbsmigals0gals1+fiommu@1c01f000mediatek,mt8195-iommu-vdo8xyz{|}~t'wbclk+wlarb@1c102000mediatek,mt8195-smi-larb  f""" wapbsmigals+ylarb@1c103000mediatek,mt8195-smi-larb0 V""  wapbsmigals+Ychosen\serial0:115200n8memory@40000000|memory@regulator-pp3300-ldo-z5regulator-fixedpp3300_ldo_z5Ch2Z2Zzregulator-pp3300-s3regulator-fixed pp3300_s3Ch2Z2ZzJregulator-pp3300-z2regulator-fixed pp3300_z2Ch2Z2Zzregulator-pp4200-z2regulator-fixed pp4200_z2Ch@@@@zregulator-pp5000-s5regulator-fixed pp5000_s5ChLK@LK@zregulator-ppvar-sysregulator-fixed ppvar_sysChregulator-5v0-usb-vbusregulator-fixed usb-vbusLK@LK@C5reserved-memory+memory@50000000shared-dma-poolP( compatibleinterrupt-parent#address-cells#size-cellsmodelgce0gce1i2c0i2c1i2c2i2c3i2c4i2c5i2c7mmc0mmc1serial0device_typeregenable-methodperformance-domainsclock-frequencycapacity-dmips-mhzcpu-idle-statesnext-level-cache#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usinterruptscpusnum-channelswakeup-delay-msmediatek,platformstatus#clock-cellsclocksclock-divclock-multclock-output-names#performance-domain-cellsranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangesmediatek,rsel-resistance-in-si-unitpinctrl-namespinctrl-0gpio-line-namespinmuxinput-enablebias-pull-upbias-disabledrive-strength-microampdrive-strengthbias-pull-downoutput-highoutput-low#power-domain-cellsclock-namesmediatek,infracfgmediatek,disable-extrstassigned-clocksassigned-clock-parentsinterrupts-extendedregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modesregulator-compatible#iommu-cells#mbox-cellsfirmware-namememory-regionmediatek,rpmsg-namepower-domainsmbox-namesmboxesmediatek,topckgenresetsreset-names#io-channel-cellsmediatek,pad-selectspi-max-frequencygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countpower-roledata-roletry-power-rolekeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymapfunction-row-physmapphysmediatek,syscon-wakeupwakeup-sourcevusb33-supplyvbus-supplybus-widthcap-mmc-highspeedcap-mmc-hw-reseths400-ds-delaymmc-hs200-1_8vmmc-hs400-1_8vno-sdiono-sdnon-removablepinctrl-1vmmc-supplyvqmmc-supplycap-sd-highspeedcd-gpiosno-mmcsd-uhs-sdr50sd-uhs-sdr104usb2-lpm-disablespi-rx-bus-widthspi-tx-bus-widthbits#phy-cellsinterrupt-namesi2c-scl-internal-delay-nsvcc-supplyhid-descr-addrpost-power-on-delay-msvdd-supplynvmem-cellsnvmem-cell-namesmediatek,smimediatek,larb-idmediatek,larbsiommusmediatek,gce-client-regmediatek,gce-eventsstdout-pathregulator-boot-onvin-supplyenable-active-highno-map