[8U(U|$mediatek,mt2712-evbmediatek,mt2712 +!7MediaTek MT2712 evaluation board =embeddedopp-table-0operating-points-v2JUopp00]#dB@opp01])׫dB@opp02]/D8@dB@opp-table-1operating-points-v2JU opp00]#dB@opp01])׫dB@opp02]/D8@dB@opp03]5w"@dB@opp04]; @dB@cpus+cpu-mapcluster0core0rcore1rcluster1core0rcpu@0vcpuarm,cortex-a35%cpuintermediate Ucpu@1vcpuarm,cortex-a35psci%cpuintermediate Ucpu@200vcpuarm,cortex-a72psci'cpuintermediate   Uidle-statespscicpu-sleep-0arm,idle-statedP'U cluster-sleep-0arm,idle-state^P 'U psci arm,psci-0.2smcdummy26m fixed-clock>NUdummyclk fixed-clock>NUoscillator-26m fixed-clockN>[clk26mU*oscillator-32k fixed-clockN>[clk32koscillator-50m fixed-clockN>[clkfpcoscillator-aud0 fixed-clockN>c.[clkaud_ext_i_0oscillator-aud1 fixed-clockN> [clkaud_ext_i_1oscillator-aud2 fixed-clockN> @[clkaud_ext_i_2oscillator-i2s0 fixed-clockN>À[clki2si0_mck_ioscillator-i2s1 fixed-clockN>À[clki2si1_mck_ioscillator-i2s2 fixed-clockN>À[clki2si2_mck_ioscillator-mclk fixed-clockN>À[clktdmin_mclk_itimerarm,armv8-timer 0n   syscon@10000000 mediatek,mt2712-topckgensysconNUsyscon@10001000 mediatek,mt2712-infracfgsysconNUsyscon@10003000mediatek,mt2712-pericfgsyscon0NUsyscfg_pctl_a@10005000%mediatek,mt2712-pctl-a-syscfgsysconPUpinctrl@1000b000mediatek,mt2712-pinctrly nU"eth_defaultU#tx_pinsGHIJKLrx_pinsNOPQRTmdio_pinsUVeth_sleepU$tx_pinsGHIJKLrx_pinsNOPQRTmdio_pinsUVusb0_iddigU)pins_iddig usb1_iddigU1pins_iddigpower-controller@10006000mediatek,mt2712-scpsyssyscon`0eihgmmmfgvencjpgdecaudiovdec/Userial@1000f000*mediatek,mt2712-uartmediatek,mt6577-uart n baudbus8  =txrx Gdisabledrtc@10011000mediatek,mt2712-rtc nspi@10013000mediatek,mt2712-spi-slave0 nspiN^ Gdisablediommu@10205000mediatek,mt2712-m4u P nbclkusyscon@10209000"mediatek,mt2712-apmixedsyssyscon Niommu@1020a000mediatek,mt2712-m4u  nbclku syscon@10220000mediatek,mt2712-mcucfgsyscon"NUinterrupt-controller@10220a80.mediatek,mt2712-sysirqmediatek,mt6577-sysirq " @Uinterrupt-controller@10510000 arm,gic-400 @QRTV n U dma-controller@110004002mediatek,mt2712-uart-dmamediatek,mt6577-uart-dma  nghijklmnopqr  apdmaUadc@11001000mediatek,mt2712-auxadcmainGokayserial@11002000*mediatek,mt2712-uartmediatek,mt6577-uart  n[ baudbus8=txrxGokayserial@11003000*mediatek,mt2712-uartmediatek,mt6577-uart0 n\ baudbus8=txrx Gdisabledserial@11004000*mediatek,mt2712-uartmediatek,mt6577-uart@ n] baudbus8=txrx Gdisabledserial@11005000*mediatek,mt2712-uartmediatek,mt6577-uartP n^ baudbus8=txrx Gdisabledpwm@11006000mediatek,mt2712-pwm` nMPf  1topmainpwm1pwm2pwm3pwm4pwm5pwm6pwm7pwm8 Gdisabledi2c@11007000mediatek,mt2712-i2c p nT  maindma+ Gdisabledi2c@11008000mediatek,mt2712-i2c  nU  maindma+ Gdisabledi2c@11009000mediatek,mt2712-i2c  nV  maindma+ Gdisabledspi@1100a000mediatek,mt2712-spi+ nvlparent-clksel-clkspi-clk Gdisablednand-controller@1100e000mediatek,mt2712-nfc n`nfi_clkpad_clk+ Gdisabledecc@1100f000mediatek,mt2712-ecc n_ nfiecc_clk GdisabledUi2c@11010000mediatek,mt2712-i2c  nW  maindma+ Gdisabledi2c@11011000mediatek,mt2712-i2c  nX  maindma+ Gdisabledi2c@11013000mediatek,mt2712-i2c 0 nZ  maindma+ Gdisabledspi@11015000mediatek,mt2712-spi+P nlparent-clksel-clkspi-clk Gdisabledspi@11016000mediatek,mt2712-spi+` nlparent-clksel-clkspi-clk Gdisabledspi@10012000mediatek,mt2712-spi+  nlparent-clksel-clkspi-clk Gdisabledspi@11018000mediatek,mt2712-spi+ nlparent-clksel-clkspi-clk Gdisabledserial@11019000*mediatek,mt2712-uartmediatek,mt6577-uart n~ baudbus8 =txrx Gdisabledstmmac-axi-config Urx-queues-config-Uqueue0>Qitx-queues-configwU queue0>iqueue1>iqueue2>iethernet@1101c000&mediatek,mt2712-gmacsnps,dwmac-4.20a nmacirqU{}'axiapbmac_mainptp_refrmii_internal("%N^=> '2Gokay ?rgmii-rxidH!S h"W x''defaultsleep#$mdiosnps,dwmac-mdio+ethernet-phy@5ethernet-phy-id0243.0d90U!mmc@11230000mediatek,mt2712-mmc# nO  *&,sourcehclksource_cgbus_clk Gdisabledmmc@11240000mediatek,mt2712-mmc$ nP c'sourcehclksource_cg Gdisabledmmc@11250000mediatek,mt2712-mmc% nQc(sourcehclksource_cg Gdisabledusb@11271000#mediatek,mt2712-mtu3mediatek,mtu3 '0( macippc nz%&nsys_ck +Gokay'(otgdefault)usb@11270000'mediatek,mt2712-xhcimediatek,mtk-xhci'mac n{ n*sys_ckref_ckGokay+t-phy@11290000.mediatek,mt2712-tphymediatek,generic-tphy-v2+)Gokayusb-phy@0*refGokayU%usb-phy@8000*refGokayU&usb-phy@8700 *refGokayU3usb@112c1000#mediatek,mt2712-mtu3mediatek,mtu3 ,0- macippc n,-.nsys_ck +Gokay/0otg%default1usb@112c0000'mediatek,mt2712-xhcimediatek,mtk-xhci,mac n n*sys_ckref_ckGokayt-phy@112e0000.mediatek,mt2712-tphymediatek,generic-tphy-v2+.Gokayusb-phy@0*refGokayU,usb-phy@8000*refGokayU-usb-phy@8700 *refGokayU.pcie@112ff000mediatek,mt2712-pcievpci/port17+ nu pcie_irq$sys_ck1ahb_ck1. Hpcie-phy1RՂ@@0 Gdisabled\`o2222interrupt-controllerU2pcie@11700000mediatek,mt2712-pcievpcipport07+ ns pcie_irq#sys_ck0ahb_ck03 Hpcie-phy0RՂ  Gdisabled\`o4444interrupt-controllerU4syscon@13000000mediatek,mt2712-mfgcfgsysconNsyscon@14000000mediatek,mt2712-mmsyssysconNU6larb@14021000mediatek,mt2712-smi-larb}566apbsmiUsmi@14022000mediatek,mt2712-smi-common 66apbsmiU5larb@14027000mediatek,mt2712-smi-larbp}76,6,apbsmiUlarb@14030000mediatek,mt2712-smi-larb}76.6.apbsmiUsmi@14031000mediatek,mt2712-smi-common6-6-apbsmiU7larb@14032000mediatek,mt2712-smi-larb }76868apbsmiUsyscon@15000000mediatek,mt2712-imgsyssysconNU8larb@15001000mediatek,mt2712-smi-larb}588apbsmiUsyscon@15010000mediatek,mt2712-bdpsyssysconNsyscon@16000000mediatek,mt2712-vdecsyssysconNU9larb@16010000mediatek,mt2712-smi-larb}599apbsmiUsyscon@18000000mediatek,mt2712-vencsyssysconNU:larb@18001000mediatek,mt2712-smi-larb}5::apbsmiUlarb@18002000mediatek,mt2712-smi-larb }5::apbsmiUsyscon@19000000!mediatek,mt2712-jpgdecsyssysconNaliases/serial@11002000memory@40000000vmemory@chosenserial0:921600n8regulator-vproc-buck0regulator-fixed vproc_buck0B@B@Uregulator-vproc-buck1regulator-fixed vproc_buck1B@B@U extcon_iddiglinux,extcon-usb-gpio " U(extcon_iddig1linux,extcon-usb-gpio "U0regulator-usb-p0-vbusregulator-fixedp0_vbusLK@LK@ s" U'regulator-usb-p1-vbusregulator-fixedp1_vbusLK@LK@ s"U/regulator-usb-p2-vbusregulator-fixedp2_vbusLK@LK@ s"U+regulator-usb-p3-vbusregulator-fixedp3_vbusLK@LK@ s"  compatibleinterrupt-parent#address-cells#size-cellsmodelchassis-typeopp-sharedphandleopp-hzopp-microvoltcpudevice_typeregclocksclock-namesproc-supplyoperating-points-v2cpu-idle-statesenable-methodentry-methodlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usarm,psci-suspend-paramclock-frequency#clock-cellsclock-output-namesinterruptsmediatek,pctl-regmapgpio-controller#gpio-cellsinterrupt-controller#interrupt-cellspinmuxdrive-strengthinput-enableinput-disablebias-disablebias-pull-up#power-domain-cellsinfracfgdmasdma-namesstatusassigned-clocksassigned-clock-parentsmediatek,infracfgmediatek,larbs#iommu-cellsdma-requests#dma-cells#io-channel-cells#pwm-cellsclock-divecc-enginesnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,prioritysnps,tx-queues-to-usesnps,tx-sched-wrrsnps,weightinterrupt-namesmac-addresspower-domainsmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrphy-modephy-handlemediatek,tx-delay-pssnps,reset-gpiosnps,reset-delays-uspinctrl-namespinctrl-0pinctrl-1reg-namesphysmediatek,syscon-wakeuprangesvbus-supplyextcondr_modewakeup-sourcemediatek,u3p-dis-msk#phy-cellsenable-manual-drdlinux,pci-domainphy-namesbus-rangeinterrupt-map-maskinterrupt-mapmediatek,smimediatek,larb-idserial0stdout-pathregulator-nameregulator-min-microvoltregulator-max-microvoltid-gpioenable-active-highregulator-always-on