8( $rockchip,rk3328-evbrockchip,rk3328 +7Rockchip RK3328 EVBaliases=/serial@ff110000E/serial@ff120000M/serial@ff130000U/i2c@ff150000Z/i2c@ff160000_/i2c@ff170000d/i2c@ff180000i/ethernet@ff540000s/ethernet@ff550000}/mmc@ff500000/mmc@ff510000/mmc@ff520000cpus+cpu@0cpuarm,cortex-a53xpsci cpu@1cpuarm,cortex-a53xpsci cpu@2cpuarm,cortex-a53xpsci cpu@3cpuarm,cortex-a53xpsci idle-states"pscicpu-sleeparm,idle-state/@Wxhxl2-cache0cacheopp-table-0operating-points-v2opp-408000000Q~@opp-600000000#F~@opp-8160000000,B@@opp-1008000000<@opp-1200000000G(@opp-1296000000M?d @analog-soundsimple-audio-cardi2sAnalog *disabledsimple-audio-card,cpu1simple-audio-card,codec1arm-pmuarm,cortex-a53-pmu0;defgF display-subsystemrockchip,display-subsystemY hdmi-soundsimple-audio-cardi2sHDMI *disabledsimple-audio-card,cpu1simple-audio-card,codec1psciarm,psci-1.0arm,psci-0.2smctimerarm,armv8-timer0;   xin24m fixed-clock_ln6|xin24mBi2s@ff000000(rockchip,rk3328-i2srockchip,rk3066-i2s ;)7i2s_clki2s_hclk  txrx *disabledi2s@ff010000(rockchip,rk3328-i2srockchip,rk3066-i2s ;*8i2s_clki2s_hclktxrx *disabledi2s@ff020000(rockchip,rk3328-i2srockchip,rk3066-i2s ;+9i2s_clki2s_hclktxrx *disabledspdif@ff030000rockchip,rk3328-spdif ;.: mclkhclk txdefault *disabledpdm@ff040000 rockchip,pdm=Rpdm_clkpdm_hclkrxdefaultsleep *disabledsyscon@ff100000&rockchip,rk3328-grfsysconsimple-mfd7io-domains"rockchip,rk3328-io-voltage-domain *disabledgpiorockchip,rk3328-grf-gpiopower-controller!rockchip,rk3328-power-controller+9power-domain@6power-domain@5 BABpower-domain@8Freboot-modesyscon-reboot-mode RB RB.RB >RBserial@ff110000&rockchip,rk3328-uartsnps,dw-apb-uart ;7&baudclkapb_pclktxrxdefault JW *disabledserial@ff120000&rockchip,rk3328-uartsnps,dw-apb-uart ;8'baudclkapb_pclktxrxdefault  !JW *disabledserial@ff130000&rockchip,rk3328-uartsnps,dw-apb-uart ;9(baudclkapb_pclktxrxdefault"JW*okayi2c@ff150000(rockchip,rk3328-i2crockchip,rk3399-i2c ;$+7 i2cpclkdefault# *disabledi2c@ff160000(rockchip,rk3328-i2crockchip,rk3399-i2c ;%+8 i2cpclkdefault$*okaypmic@18rockchip,rk805 %;_|xin32krk805-clkout2default&a''''((regulatorsDCDC_REG1 vdd_logic 4 +regulator-state-mem=UB@DCDC_REG2vdd_arm 4 +regulator-state-mem=U~DCDC_REG3vcc_ddr+regulator-state-mem=DCDC_REG4vcc_io2Z2Z+(regulator-state-mem=U2ZLDO_REG1vcc_18w@w@+regulator-state-mem=Uw@LDO_REG2 vcc18_emmcw@w@+regulator-state-mem=Uw@LDO_REG3vdd_10B@B@+regulator-state-mem=UB@i2c@ff170000(rockchip,rk3328-i2crockchip,rk3399-i2c ;&+9 i2cpclkdefault) *disabledi2c@ff180000(rockchip,rk3328-i2crockchip,rk3399-i2c ;'+: i2cpclkdefault* *disabledspi@ff190000(rockchip,rk3328-spirockchip,rk3066-spi ;1+ spiclkapb_pclk txrxdefault+,-. *disabledwatchdog@ff1a0000 rockchip,rk3328-wdtsnps,dw-wdt ;(pwm@ff1b0000rockchip,rk3328-pwm< pwmpclkdefault/q *disabledpwm@ff1b0010rockchip,rk3328-pwm< pwmpclkdefault0q *disabledpwm@ff1b0020rockchip,rk3328-pwm < pwmpclkdefault1q *disabledpwm@ff1b0030rockchip,rk3328-pwm0 ;2< pwmpclkdefault2q *disableddma-controller@ff1f0000arm,pl330arm,primecell@;| apb_pclkthermal-zonessoc-thermal3tripstrip-point0ppassivetrip-point1Lpassive4soc-crits criticalcooling-mapsmap040 tsadc@ff250000rockchip,rk3328-tsadc% ;:$,P$tsadcapb_pclkinitdefaultsleep56A5KB Rtsadc-apb^7k*okay3efuse@ff260000rockchip,rk3328-efuse&P+> pclk_efuse id@7cpu-leakage@17logic-leakage@19cpu-version@1aCadc@ff280000.rockchip,rk3328-saradcrockchip,rk3399-saradc( ;P%saradcapb_pclkKV Rsaradc-apb *disabledgpu@ff300000"rockchip,rk3328-maliarm,mali-4500T;ZW]XY[\"gpgpmmupppp0ppmmu0pp1ppmmu1 buscoreKfiommu@ff330200rockchip,iommu3 ;` aclkiface *disablediommu@ff340800rockchip,iommu4@ ;bF aclkiface *disabledvideo-codec@ff350000rockchip,rk3328-vpu5 ; vdpuF aclkhclk89iommu@ff350800rockchip,iommu5@ ; F aclkiface98video-codec@ff360000*rockchip,rk3328-vdecrockchip,rk3399-vdec6 ; BABaxiahbcabaccoreAB ,ׄׄ:9iommu@ff360480rockchip,iommu 6@6@ ;JB aclkiface9:vop@ff370000rockchip,rk3328-vop7> ; x;aclk_vopdclk_vophclk_vopK Raxiahbdclk; *disabledport+ endpoint@0<Aiommu@ff373f00rockchip,iommu7? ; ; aclkiface *disabled;hdmi@ff3c0000rockchip,rk3328-dw-hdmi<J;#GFiahbisfrcec= hdmidefault >?@^7 *disabledports+port@0endpointA<port@1codec@ff410000rockchip,rk3328-codecA* pclkmclk^7 *disabledphy@ff430000rockchip,rk3328-hdmi-phyC ;SBysysclkrefoclkrefpclk |hdmi_phy_C  cpu-version1 *disabled=clock-controller@ff440000(rockchip,rk3328-crurockchip,crusysconD^7_<x=&'(ABDC"\5H4$IzBBB|,n6n6n6n6#FLGрxhxhрxhxhsyscon@ff450000.rockchip,rk3328-usb2phy-grfsysconsimple-mfdE+usb2phy@100rockchip,rk3328-usb2phyBphyclk |usb480m_phy_{ID*okayDotg-port1$;;<=otg-bvalidotg-idlinestate*okayUhost-port1 ;> linestate*okayVmmc@ff5000000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcP@ ;  =!JNbiuciuciu-driveciu-sample`kр*okayydefaultEFGHImmc@ff5100000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcQ@ ;  >"KObiuciuciu-driveciu-sample`kр*okayyJdefault KLMmmc@ff5200000rockchip,rk3328-dw-mshcrockchip,rk3288-dw-mshcR@ ; ?#LPbiuciuciu-driveciu-sample`kр*okayydefault NOPethernet@ff540000rockchip,rk3328-gmacT ;macirq8dWXZYMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macKc Rstmmaceth^7 *disabledethernet@ff550000rockchip,rk3328-gmacU^7 ;macirq8TSSUVIstmmacethmac_clk_rxmac_clk_txclk_mac_refaclk_macpclk_macclk_macphyKb Rstmmacethrmii Qoutput*okay%R0eITmdiosnps,dwmac-mdio+ethernet-phy@04ethernet-phy-id1234.d400ethernet-phy-ieee802.3-c22VKddefaultSTDQusb@ff5800002rockchip,rk3328-usbrockchip,rk3066-usbsnps,dwc2X ;MotgVotg^p@ U  usb2-phy*okayusb@ff5c0000 generic-ehci\ ; NDV usb*okayusb@ff5d0000 generic-ohci] ; NDV usb*okayusb@ff600000rockchip,rk3328-dwc3snps,dwc3` ;C`aref_clksuspend_clkbus_clkVotg utmi_wide, *disabledinterrupt-controller@ff811000 arm,gic-400EV@ @ `  ; crypto@ff060000rockchip,rk3328-crypto@ ;PQ;hclk_masterhclk_slavesclkKD Rcrypto-rstpinctrlrockchip,rk3328-pinctrl^7+kgpio@ff210000rockchip,gpio-bank! ;3VEdgpio@ff220000rockchip,gpio-bank" ;4VEcgpio@ff230000rockchip,gpio-bank# ;5VE%gpio@ff240000rockchip,gpio-bank$ ;6VEpcfg-pull-uprYpcfg-pull-downapcfg-pull-noneWpcfg-pull-none-2ma`pcfg-pull-up-2marpcfg-pull-up-4marZpcfg-pull-none-4ma]pcfg-pull-down-4mapcfg-pull-none-8ma[pcfg-pull-up-8mar\pcfg-pull-none-12ma ^pcfg-pull-up-12mar _pcfg-output-highpcfg-output-lowpcfg-input-highrXpcfg-inputi2c0i2c0-xfer WW#i2c1i2c1-xfer WW$i2c2i2c2-xfer  WW)i2c3i2c3-xfer WW*i2c3-pins WWhdmi_i2chdmii2c-xfer WW?pdm-0pdmm0-clkWpdmm0-fsyncWpdmm0-sdi0Wpdmm0-sdi1Wpdmm0-sdi2Wpdmm0-sdi3Wpdmm0-clk-sleepXpdmm0-sdi0-sleepXpdmm0-sdi1-sleepXpdmm0-sdi2-sleepXpdmm0-sdi3-sleepXpdmm0-fsync-sleepXtsadcotp-pin W5otp-out W6uart0uart0-xfer  WYuart0-cts Wuart0-rts Wuart0-rts-pin Wuart1uart1-xfer WYuart1-ctsW uart1-rtsW!uart1-rts-pinWuart2-0uart2m0-xfer WYuart2-1uart2m1-xfer WY"spi0-0spi0m0-clkYspi0m0-cs0 Yspi0m0-tx Yspi0m0-rx Yspi0m0-cs1 Yspi0-1spi0m1-clkYspi0m1-cs0Yspi0m1-txYspi0m1-rxYspi0m1-cs1Yspi0-2spi0m2-clkY+spi0m2-cs0Y.spi0m2-txY,spi0m2-rxY-i2s1i2s1-mclkWi2s1-sclkWi2s1-lrckrxWi2s1-lrcktxWi2s1-sdiWi2s1-sdoWi2s1-sdio1Wi2s1-sdio2Wi2s1-sdio3Wi2s1-sleepXXXXXXXXXi2s2-0i2s2m0-mclkWi2s2m0-sclkWi2s2m0-lrckrxWi2s2m0-lrcktxWi2s2m0-sdiWi2s2m0-sdoWi2s2m0-sleep`XXXXXXi2s2-1i2s2m1-mclkWi2s2m1-sclkWi2sm1-lrckrxWi2s2m1-lrcktxWi2s2m1-sdiWi2s2m1-sdoWi2s2m1-sleepPXXXXXspdif-0spdifm0-txWspdif-1spdifm1-txWspdif-2spdifm2-txWsdmmc0-0sdmmc0m0-pwrenZsdmmc0m0-pinZsdmmc0-1sdmmc0m1-pwrenZsdmmc0m1-pinZesdmmc0sdmmc0-clk[Esdmmc0-cmd\Fsdmmc0-dectnZGsdmmc0-wrprtZsdmmc0-bus1\sdmmc0-bus4@\\\\Hsdmmc0-pinsZZZZZZZZsdmmc0extsdmmc0ext-clk]sdmmc0ext-cmdZsdmmc0ext-wrprtZsdmmc0ext-dectnZsdmmc0ext-bus1Zsdmmc0ext-bus4@ZZZZsdmmc0ext-pinsZZZZZZZZsdmmc1sdmmc1-clk [Msdmmc1-cmd \Lsdmmc1-pwren\sdmmc1-wrprt\sdmmc1-dectn\sdmmc1-bus1\sdmmc1-bus4@\\\\Ksdmmc1-pins Z ZZZZZZZZemmcemmc-clk^Nemmc-cmd_Oemmc-pwrenWemmc-rstnoutWemmc-bus1_emmc-bus4@____emmc-bus8________Ppwm0pwm0-pinW/pwm1pwm1-pinW0pwm2pwm2-pinW1pwmirpwmir-pinW2gmac-1rgmiim1-pins` [ ]][]]] ] ][ []][[[ [][[[[rmiim1-pins`^```` ` `^ ^ W WWWWWgmac2phyfephyled-speed10Wfephyled-duplexWfephyled-rxm1WSfephyled-txm1Wfephyled-linkm1WTtsadc_pintsadc-int Wtsadc-pin Whdmi_pinhdmi-cecW>hdmi-hpda@cif-0dvp-d2d9-m0WWWWW W W WWWWWcif-1dvp-d2d9-m1WWWWWWWWWWWWpmicpmic-int-lY&sdio-pwrseqwifi-enable-hWbchosenserial2:1500000n8dc-12vregulator-fixeddc_12v+fsdio-pwrseqmmc-pwrseq-simpledefaultb cJsdmmc-regulatorregulator-fixed ddefaultevcc_sd2Z2Z(Ivcc-sysregulator-fixedvcc_sys+LK@LK@f'vcc-phy-regulatorregulator-fixedvcc_phy+R compatibleinterrupt-parent#address-cells#size-cellsmodelserial0serial1serial2i2c0i2c1i2c2i2c3ethernet0ethernet1mmc0mmc1mmc2device_typeregclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientenable-methodnext-level-cacheoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namestatussound-daiinterruptsinterrupt-affinityports#clock-cellsclock-frequencyclock-output-namesclock-namesdmasdma-names#sound-dai-cellspinctrl-namespinctrl-0pinctrl-1gpio-controller#gpio-cells#power-domain-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loaderreg-io-widthreg-shiftrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onregulator-on-in-suspendregulator-suspend-microvolt#pwm-cellsarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontributionassigned-clocksassigned-clock-ratespinctrl-2resetsreset-namesrockchip,grfrockchip,hw-tshut-temp#thermal-sensor-cellsrockchip,efuse-sizebits#io-channel-cellsinterrupt-names#iommu-cellsiommuspower-domainsremote-endpointphysphy-namesnvmem-cellsnvmem-cell-names#phy-cells#reset-cellsassigned-clock-parentsfifo-depthmax-frequencybus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablesnps,txpblphy-modephy-handleclock_in_outphy-supplyassigned-clock-ratephy-is-integrateddr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy_typesnps,dis-del-phy-power-chg-quirksnps,dis_enblslpm_quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis_u3_susphy_quirk#interrupt-cellsinterrupt-controllerrangesbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathreset-gpiosgpiovin-supply